Stressed Dielectric Layer for Transistor Channel Mobility

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Solution Overview

Problem

Existing methods for forming semiconductor structures with stressed channel regions face challenges in effectively transmitting stress to the substrate, leading to insufficient stress in the channel regions, which can negatively impact charge carrier mobility and is not adaptable for transistors of different types, potentially harming performance or being detrimental.

Innovation Solution

A method involving the formation of a thicker dielectric layer with intrinsic stress over an etch stop layer, accompanied by a protective layer to prevent moisture intrusion and maintain stress, allowing for enhanced stress transmission and tailored stress application to individual transistor types.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stress or pressure

If a thin dielectric layer with intrinsic stress is formed over the transistor element, then the manufacturing process is simple, but the stress transmission to the substrate is insufficient, leading to inadequate charge carrier mobility improvement

Engineering Contradiction:
Improvestress in channel regionVSAvoiddielectric layer structure
Core Design Contradiction:
Stress or pressureVSDevice complexity

Solution Approach 1:

The patent divides the dielectric layer into multiple segments: a first dielectric layer in direct contact with the transistor element that provides stress transmission, and a second dielectric layer positioned above that provides protection. This segmentation allows the stress-transmitting function and protection function to be separated, enabling the thin first layer to effectively transmit stress while the thicker second layer provides adequate protection without interfering with stress transmission.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary structure (the two-layer dielectric configuration) where the first dielectric layer acts as a mediator between the transistor element and the second dielectric layer. This intermediary arrangement allows stress to be transmitted from the first dielectric layer to the substrate while the second dielectric layer provides protective functions, thus resolving the contradiction between maintaining simplicity and achieving sufficient stress transmission.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the dielectric layer is made thicker to improve protection, then protection effectiveness increases, but stress transmission to the substrate is reduced

Engineering Contradiction:
Improveprotection of dielectric layerVSAvoidstress transmission to substrate
Core Design Contradiction:
ReliabilityVSStress or pressure

Solution Approach 1:

The patent segments the protective function and stress transmission function into different layers. The first dielectric layer, being thin, effectively transmits stress to the substrate. The second dielectric layer, being thicker, provides enhanced protection. This segmentation resolves the contradiction by assigning different thicknesses to different layers based on their specific functions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by giving different properties to different parts of the dielectric structure. The first dielectric layer has properties optimized for stress transmission (thin thickness, specific material composition), while the second dielectric layer has properties optimized for protection (greater thickness, different material composition). This local differentiation allows each layer to excel at its specific function without compromising the other.

Inventive Principle:
Principle #3Local quality

3Adaptability or versatility

If a single dielectric layer with intrinsic stress is used, then the manufacturing process is simple, but it cannot provide tailored stress for different transistor types

Engineering Contradiction:
Improvestress application for different transistor typesVSAvoiddielectric layer configuration
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by enabling different stress characteristics in different regions. The first dielectric layer can be formed with stress characteristics optimized for the underlying transistor type, while the second dielectric layer provides additional protection. This allows tailored stress application to different transistor types (P-type or N-type) without significantly increasing manufacturing complexity, as the stress tailoring is achieved through material selection and layer configuration rather than complex processing.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach increases the stress influence on the semiconductor structure, improving charge carrier mobility in the channel region and ensuring that the stress benefits one transistor type without harming the other, thus enhancing the performance of both P-type and N-type transistors.

Implementation Method 1

A first dielectric layer with intrinsic stress is formed over an etch stop layer

Methodology Applied
Scientific EffectIntrinsic stress: Stress Relaxation

Implementation Method 2

a protective layer adapted to reduce an intrusion of moisture into the first dielectric layer is formed over the first dielectric layer

Methodology Applied
Scientific EffectMoisture barrier: Permeation

Data Source

PatentUS7858531B2Method of forming a semiconductor structure comprising a field effect transistor having a stressed channel region
Publication Date: 2010.12.28 ADVANCED MICRO DEVICES INC
  • US7858531B2 patent drawing
  • US7858531B2 patent drawing
  • US7858531B2 patent drawing

AI summary

A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising at least one transistor element. An etch stop layer is formed over the transistor element. A stressed first dielectric layer is formed over the etch stop layer. A protective layer adapted to reduce an intrusion of moisture into the first dielectric layer is formed over the first dielectric layer. At least one electrical connection to the transistor element is formed. At least a portion of the protective layer remains over the first dielectric layer after completion of the formation of the at least one electrical connection.