Stressed FET Gate Structure for Electron Density Control
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Solution Overview
Problem
Existing field-effect transistors (FETs) face challenges in integrating depletion-type (D-type), enhancement-type (E-type), and low-noise transistors on a common substrate due to differences in their internal structure and electrical characteristics, leading to increased gate capacitance and reduced electron density, which affects reliability and performance, especially in short-channel FETs.
Innovation Solution
A gate structure for FETs incorporating a piezoelectric active layer with a recess and stressed dielectric layers that apply tensile or compressive stress to modify the electron density via the piezoelectric effect, allowing integration of various transistor types without altering the active layer, thus maintaining electron density and reducing gate capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If local gate recesses are used to bring the gate closer to the channel region, then the blocking field control is improved, but the electron density below the gate in the on-state is reduced
Solution Approach 1:
The patent applies different stress states (tensile or compressive) to specific dielectric layers in the region around the contact element, creating local variations in electron density through the piezoelectric effect. This allows the blocking field control to be improved in the gate region while maintaining electron density in the channel region through selective stress application.
Solution Approach 2:
The patent changes the physical state of dielectric layers by applying tensile or compressive stress (|σ| > 200 MPa) to modify the electron density in the active layer through the piezoelectric effect. This parameter change allows control of the blocking field without permanently altering the active layer structure or reducing electron density in the on-state.
2Reliability
If the gate is positioned closer to the 2DEG to achieve self-blocking, then the pinch-off voltage is improved, but the gate capacitance is significantly increased
Solution Approach 1:
The patent uses stress-induced piezoelectric effects to modify electron density and achieve self-blocking capability without physically moving the gate closer to the 2DEG. By applying tensile or compressive stress to dielectric layers, the pinch-off voltage is controlled while maintaining acceptable gate capacitance levels.
3Reliability
If local gate recesses or complex p-gate structures are used to bring the gate closer, then the self-blocking behavior is improved, but the electron density under the gate in the on-state is negatively affected
Solution Approach 1:
The patent applies stress to dielectric layers specifically in the region around the contact element, creating local electron density modifications through the piezoelectric effect. This enables self-blocking behavior to be achieved while maintaining electron density in the channel region, as the stress effect is localized and reversible.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the integration of D-type, E-type, and LN-type transistors on a common substrate with improved reliability, reduced gate capacitance, and enhanced switching speeds, suitable for monolithic microwave integrated circuits (MMICs) and transceiver integration.
Implementation Method 1
at least one layer arranged above the active layer is formed in the area around the contact element under tensile or compressive stress with a normal stress |σ| > 200 MPa, wherein a resultant force is applied at the interface between the passivation layer and the active layer via the individual stresses in the area around the contact element, which influences the electron density in the active layer in the area below the contact element via the piezoelectric effect
Data Source
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AI summary
The present invention relates to a gate structure and to a method for producing same. In particular, the present invention relates to a gate structuring of a field effect transistor (FET), wherein the field effect transistor, for the same active layer, can be constructed as depletion type (or "D-type"), as enhancement type (or "E-type") and/or as low noise type (or "LN-type") on a common substrate base in a uniform method. The gate structure according to the invention comprises a substrate; a piezoelectric active layer (112, 212) arranged on the substrate (110, 210); a passivation layer (120, 220) arranged on the active layer (112, 212), wherein the passivation layer (120, 220) has a cutout (122, 222) extending through the entire passivation layer (120, 220) in the direction of the active layer (112, 212); a contact element (140, 240) arranged within the cutout (122, 222), wherein the contact element (140, 240) extends from the active layer (112, 212) to above the passivation layer (120, 220); and a cover layer (150, 250) covering the contact element (140, 240) above the passivation layer (120, 220); wherein at least one layer arranged above the active layer, in the region around the contact element, is embodied under tensile or compressive stress with a normal stress |σ| > 200 MPa, wherein by way of the individual stresses in the region around the contact element a resultant force is set at the interface between passivation layer and active layer, which force influences the electron density in the active layer in the region below the contact element by way of the piezoelectric effect.