Stressed FET With Segmented SiGe Regions
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Solution Overview
Problem
Current field effect transistors (FETs) do not effectively enhance the mobility of majority carrier holes, which limits their current carrying capability, despite techniques like embedding SiGe to apply compressive stress, none have achieved the potential mobility enhancement.
Innovation Solution
A stressed field effect transistor is fabricated with a silicon substrate, featuring a gate insulator and gate electrode defining a channel region, with a shallow undoped silicon germanium region embedded close to the channel and a deeper impurity-doped silicon germanium region spaced apart, applying uniaxial compressive stress to enhance hole mobility without adverse effects from boron doping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If embedded SiGe is used to apply compressive stress to enhance hole mobility, then hole mobility is improved, but boron doping causes adverse effects and strain relaxation
Solution Approach 1:
The device is segmented into distinct functional regions: a first SiGe region for stress application and a second SiGe region for doping, separated by a spacer. This segmentation allows the doped region to provide stress enhancement without the boron doping adversely affecting the channel or causing strain relaxation in the undoped stress-applying region.
Solution Approach 2:
Different regions of the device are assigned different material properties: the first SiGe region is undoped to preserve strain and apply compressive stress, while the second SiGe region is boron-doped to provide additional stress without needing to be in direct contact with the channel. Each region has optimized local quality for its specific function.
2Speed
If doped silicon germanium is embedded close to the channel, then stress is applied to enhance mobility, but channel encroachment occurs
Solution Approach 1:
An undoped SiGe region acts as an intermediary between the doped SiGe region and the silicon channel. This intermediary allows the doped region to be positioned close to the channel for effective stress application while preventing direct contact that would cause channel encroachment and adverse doping effects.
3Speed
If multiple silicon germanium regions are embedded, then stress distribution is improved, but device complexity increases
Solution Approach 1:
Multiple SiGe regions are merged into a single integrated structure with a consistent orientation relationship to the silicon channel. The first and second SiGe regions are both oriented at approximately 45 degrees to the channel, merging their stress effects constructively while maintaining a unified fabrication approach rather than treating them as separate complex components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases the mobility of majority carrier holes in the channel region, improving the performance of P-channel FETs by preserving strain and avoiding channel encroachment, thus enhancing the transconductance and current carrying capability.
Implementation Method 1
A silicon germanium (SiGe) crystal has a greater lattice constant than the lattice constant of a silicon crystal, and consequently the presence of embedded SiGe causes a deformation of the silicon matrix that, in turn, compresses the silicon in the channel region
Implementation Method 2
A first undoped silicon germanium layer is epitaxially embedded into the silicon layer and aligned with the gate electrode. A second impurity doped silicon germanium layer is epitaxially embedded into the silicon layer and spaced apart from the gate electrode
Data Source
AI summary
A stressed field effect transistor and methods for its fabrication are provided. The field effect transistor comprises a silicon substrate with a gate insulator overlying the silicon substrate. A gate electrode overlies the gate insulator and defines a channel region in the silicon substrate underlying the gate electrode. A first silicon germanium region having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate.