Stressed Gate Recess Structure for Threshold Control in FETs
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Solution Overview
Problem
Existing technologies face challenges in integrating depletion-type, enhancement-type, and low-noise-type transistors on a shared substrate base without influencing electron density in the on-state, leading to reduced maximum current and increased gate capacity, which impairs microwave properties.
Innovation Solution
A gate structure with a piezoelectric active layer and a passivation layer that includes a recess with a contact element, where at least one layer above the active layer is tensile or compressively stressed to influence electron density via the piezoelectric effect, allowing for variable threshold voltage selection without altering electron density in the on-state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If local gate recesses are used in the semiconductor material to bring the gate closer to the channel area, then the control capability over the channel current is improved, but the electron density below the gate in the on-state is negatively influenced and the gate capacity increases
Solution Approach 1:
The patent applies tensile or compressive stress to at least one layer above the active layer to influence the electron density in the active layer below the gate contact through the piezoelectric effect. This parameter change allows control of the electron density without modifying the gate geometry or bringing the gate closer to the channel, thus avoiding the harmful side effects of increased gate capacity while maintaining improved control capability.
Solution Approach 2:
The patent replaces the mechanical approach of creating physical gate recesses in the semiconductor material with a stress application mechanism. Instead of mechanically altering the gate position or channel geometry, the invention uses applied stress to the layers above the active layer to achieve the desired electronic effect through the piezoelectric coupling, thereby avoiding the detrimental effects on electron density and gate capacity.
2Reliability
If p-gate structures are used to bring the gate closer to the channel area, then the control capability is improved, but the construction complexity increases and electron density is negatively influenced
Solution Approach 1:
The patent uses stress application as a parameter change to influence electron density and improve control capability without requiring complex p-gate structures. By applying tensile or compressive stress to layers above the active layer, the invention achieves the desired electrical effect through a simpler construction that does not involve additional doped regions or complex gate geometries.
Solution Approach 2:
The patent substitutes the complex mechanical and structural approach of p-gate formation with a stress application mechanism. Instead of creating additional doped regions and complex gate structures, the invention applies stress to the existing layers to achieve the same electrical control effect, thereby reducing construction complexity while maintaining improved control capability.
3Reliability
If the gate electrode is brought very close to the 2DEG to deplete the channel at 0 V gate voltage, then self-blocking behavior is achieved, but the maximum electron concentration is reduced and gate capacity significantly increases
Solution Approach 1:
The patent applies stress to at least one layer above the active layer to influence the electron density in the active layer through the piezoelectric effect. This parameter change enables control of the electron concentration and depletion behavior without physically bringing the gate electrode closer to the 2DEG, thus achieving self-blocking behavior while maintaining maximum electron concentration and avoiding significant gate capacity increase.
4Adaptability or versatility
If various transistor types are integrated on a shared substrate without influencing electron density, then manufacturing versatility is improved, but parasitic resistances and leakage currents increase
Solution Approach 1:
The patent applies stress locally to at least one layer above the active layer in specific regions to influence the electron density and threshold voltage in those areas. This local quality change allows different transistor types (depletion-type, enhancement-type, low-noise-type) to be integrated on a shared substrate with optimized electrical properties in each region, thereby reducing parasitic resistances and leakage currents while maintaining manufacturing versatility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the integration of various transistor types on a shared substrate with improved electronic properties, reducing parasitic resistances and leakage currents, and enhancing switching speeds and reliability.
Implementation Method 1
wherein via the individual stresses in the area around the contact element, a resulting force on the boundary area between the passivation layer and the active layer is set, which influences via the piezoelectric effect the electron density in the active layer in the area below the contact element
Data Source
AI summary
The present invention relates to a gate structure and a method for its production. In particular, the present invention relates to agate structuring of a field effect transistor (FET), wherein the field effect transistor with the same active layer can be constructed as a depletion type, or D-type, as an enhancement type, or E-type, and as a low noise type, or LN-type, on a shared substrate base using a uniform method.The gate structure according to the invention comprises a substrate; a piezoelectric active layer (112, 212) disposed on the substrate (110, 210); a passivation layer (120, 220) disposed on the active layer (112, 212), wherein the passivation layer (120, 220) has a recess (122, 222) that extends through the entire passivation layer (120, 220) in the direction of the active layer (112, 212); a contact element (140, 240) disposed within the recess (122, 222), wherein the contact element (140, 240) extends from the active layer (112, 212) to above the passivation layer (120, 220); and a cover layer (150, 250) that covers the contact element (140, 240) above the passivation layer (120, 220); wherein at least one layer disposed above the active layer is tensile stressed or compressively stressed in the area around the contact element, with a normal tension of |σ|>200 MPa, wherein via the individual stresses in the area around the contact element, a resulting force on the boundary area between the passivation layer and the active layer is set, which influences via the piezoelectric effect the electron density in the active layer in the area below the contact element.