Stressed Metal Gate for FinFET Strain Engineering
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Solution Overview
Problem
The manufacturing of finFETs and FDSOI MOSFETs is hindered by the small dimensions required for the fin or Si film, leading to significant variations in device performance due to carrier scattering caused by roughness of conducting interfaces, which limits further scaling of conventional planar bulk CMOS devices.
Innovation Solution
A method involving the formation of a tuned, stressed metal gate on a high-k dielectric layer over a fin structure, which applies strain to the Si film to counteract variations in film thickness and roughness, thereby stabilizing the band structure and reducing carrier scattering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the fin or Si film dimensions are reduced to achieve thin film architecture benefits, then gate control is improved, but device performance variations increase due to carrier scattering from interface roughness
Solution Approach 1:
The patent applies strain engineering by introducing a stressed metal gate layer with controlled stress parameters (tensile or compressive stress) to modify the band structure of the Si film. This parameter change compensates for quantum confinement effects and reduces carrier scattering at rough interfaces, thereby improving device performance uniformity while maintaining the benefits of thin film architecture
Solution Approach 2:
The patent employs a composite gate structure consisting of a high-k dielectric layer combined with a stressed metal gate layer. This composite material approach allows simultaneous achievement of excellent gate control (from the high-k dielectric) and performance stabilization (from the stressed metal layer that compensates for interface roughness effects)
2Productivity
If conventional planar bulk CMOS devices are scaled down, then device density increases, but performance degrades due to short channel effects and carrier scattering
Solution Approach 1:
The patent transitions from conventional planar bulk CMOS to thin film architecture with vertical fins or fully depleted SOI structures. This dimensional change enables superior gate control through the thin Si film while the stressed metal gate further enhances performance by compensating for quantum confinement and interface roughness effects, allowing aggressive scaling without performance degradation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces threshold voltage fluctuations and enhances carrier mobility by compensating for quantum confinement effects, improving device performance and enabling more aggressive scaling of device dimensions without performance degradation.
Implementation Method 1
forming a tuned, stressed metal gate on the dielectric layer... applies strain to the Si film to counteract variations in film thickness and roughness
Implementation Method 2
forming a high k dielectric layer on a portion of the oxide layer and on a portion of the fin
Data Source
AI summary
The present disclosure provides various embodiments of a semiconductor device and method of fabricating the semiconductor device. An exemplary semiconductor device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack includes a gate dielectric layer disposed over the semiconductor substrate and a tuned, stressed metal gate layer disposed over the gate dielectric layer. The tuned, stressed metal gate layer includes a stress that distributes strain differently to portions of the semiconductor substrate having different surface characteristics. In an example, the gate stack is disposed over a portion of a fin of the semiconductor substrate, and the fin has a varying thickness, providing a fin with a roughened surface. The tuned, stressed metal gate layer includes a stress that distributes strain differently to portions of the fin having different thicknesses.