Stressed Semiconductor Layer Formation via Selective Trench Viscosity Control

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Solution Overview

Problem

Existing transistor processing methods result in non-optimal stress in semiconductor layers, affecting the performance of p-channel and n-channel MOS transistors, as they often introduce stress in a manner that does not maximize hole or electron mobility.

Innovation Solution

A method involving the formation of uniaxial stress in semiconductor layers by creating isolation trenches in specific directions, filling them with insulating material, and adjusting the viscosity of the material through atomic implantation or annealing to optimize stress distribution, specifically for p-channel and n-channel transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If existing transistor processing methods are used to form semiconductor layers, then transistors can be manufactured with standard processes, but the stress in the channel region is non-optimal leading to reduced hole or electron mobility

Engineering Contradiction:
Improvetransistor performanceVSAvoidstress optimization
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies local quality by selectively introducing stress into specific regions of the semiconductor layer. By forming isolation trenches only in certain areas and filling them with stress-inducing material, the invention creates localized stress fields that optimize hole mobility in PMOS channels and electron mobility in NMOS channels without requiring global process changes.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes physical parameters by controlling the stress state of the semiconductor layer. By adjusting the type of material deposited in isolation trenches and controlling deposition conditions, the invention modifies the stress parameter (tensile or compressive) to optimize charge carrier mobility. The stress magnitude and direction are controlled through material selection and layer thickness adjustments.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If isolation trenches are filled with insulating material to define transistor dimensions, then transistor geometry is properly established, but the viscosity of the insulating material affects stress distribution in the semiconductor layer

Engineering Contradiction:
Improvetransistor dimension definitionVSAvoidviscosity control process
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by controlling the viscosity of insulating material before it is deposited into isolation trenches. By adjusting deposition parameters or pre-treating the material, the invention ensures optimal stress transfer to the semiconductor layer while maintaining precise trench filling. This preliminary control of material properties simplifies subsequent processing steps.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances charge carrier mobility in transistors by optimizing stress distribution, leading to improved switching speed and performance.

Implementation Method 1

decreasing the viscosity of the insulating material in the first isolation trenches by implanting atoms of a first material into the first isolation trenches

Methodology Applied
Scientific EffectViscosity decrease through atomic implantation:

Implementation Method 2

temporally decreasing, by annealing, the viscosity of the insulator layer while maintaining the stress in the semiconductor layer

Methodology Applied
Scientific EffectAnnealing: Annealing

Data Source

PatentUS9543214B2Method of forming stressed semiconductor layer
Publication Date: 2017.01.10 STMICROELECTRONICS INT NV
  • US9543214B2 patent drawing
  • US9543214B2 patent drawing
  • US9543214B2 patent drawing

AI summary

The invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a semiconductor structure having a stressed semiconductor layer, one or more first isolation trenches in a first direction for delimiting a first dimension of at least one transistor to be formed in said semiconductor structure; forming, in the semiconductor structure, one or more second isolation trenches in a second direction for delimiting a second dimension of the at least one transistor, the first and second isolation trenches being at least partially filled with an insulating material; and before or after the formation of the second isolation trenches, decreasing the viscosity of the insulating material in the first isolation trenches by implanting atoms of a first material into the first isolation trenches, wherein atoms of the first material are not implanted into the second isolation trenches.