Stressed SOI Body Contacts for CMOS Carrier Mobility
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Solution Overview
Problem
Current CMOS technology faces limitations in device performance due to parasitic resistances and capacitances, which can be addressed by selectively applying mechanical stress to channel regions and body contacts in integrated circuits to enhance carrier mobility, but existing methods struggle to apply the optimal stress types (compressive or tensile) to specific transistor devices effectively.
Innovation Solution
The method involves forming integrated circuits with semiconductor-on-insulator (SOI) body contacts that are selectively stressed, where PMOS transistor devices have a channel region under compressive longitudinal stress and a body contact under tensile lateral stress, while NMOS devices have a channel region and body contact under tensile lateral stress, using stress films to apply these stresses without adding additional processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If mechanical stress is applied to channel regions to improve carrier mobility, then device performance is improved, but it becomes difficult to apply optimal stress types (compressive or tensile) to specific transistor devices selectively
Solution Approach 1:
The patent divides the stress application into separate components: stress films are selectively formed over specific transistor regions (PMOS or NMOS) to provide longitudinal stress to channel regions, while stress liners are selectively formed over body contact regions to provide lateral stress. This segmentation allows independent optimization of stress types for different device regions and transistor types.
Solution Approach 2:
Different stress conditions are applied to different locations: compressive stress films are formed over PMOS channel regions while tensile stress films are formed over NMOS channel regions. Similarly, tensile stress liners are formed over body contact regions. This local quality approach ensures each region receives the optimal stress type for its specific function.
2Reliability
If stress films and stress liners are selectively formed to apply different stresses to channel and body contact regions, then carrier mobility is optimized, but processing complexity increases
Solution Approach 1:
The patent combines stress film formation and stress liner formation into a unified processing sequence that leverages existing fabrication steps. Stress films are formed using standard CVD or PECVD processes integrated into the existing flow, and stress liners are deposited using ALD or CVD processes that are already part of the fabrication sequence. This merging approach minimizes additional processing complexity while achieving dual stress application.
Solution Approach 2:
The stress films and stress liners serve multiple functions: they provide mechanical stress to improve carrier mobility, act as protective layers during subsequent processing, and can be selectively removed or retained based on device requirements. This multi-functionality reduces the need for additional dedicated processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of integrated circuits by optimizing carrier mobility for both NMOS and PMOS devices, enhancing drive current without increasing processing complexity, thus overcoming the limitations of existing scaling obstacles in CMOS technology.
Implementation Method 1
the application of mechanical stress on channel regions can substantially improve or degrade the mobility of electrons and holes in a semiconductor
Implementation Method 2
selectively applying a second stress to the body contact in a lateral direction perpendicular to the longitudinal direction
Data Source
AI summary
Integrated circuits with selectively stressed semiconductor-on-insulator (SOI) body contacts and methods for fabricating integrated circuits with selectively stressed SOI body contacts are provided. An exemplary method for fabricating an integrated circuit includes forming a channel region and a body contact overlying and/or in an SOI substrate. Further, the method includes selectively applying a first stress to the source/drain region in a longitudinal direction. Also, the method includes selectively applying a second stress to the body contact in a lateral direction perpendicular to the longitudinal direction.