Stressed SOI Transistor Structure With Selective Oxidation Isolation

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Solution Overview

Problem

There is a need to improve the performance and maintain constraints in constrained channel region transistors, particularly during the manufacturing process of electronic chips, and to enhance the manufacturing processes for such chips, including those with phase-change memory circuits.

Innovation Solution

A method involving the formation of semiconductor layers with specific oxidized portions and stress-inducing steps, such as epitaxial silicon-germanium growth, followed by heat treatment, to create compressive stresses in the channel-forming regions, and the integration of field-effect transistors and phase-change memory points within a silicon-on-insulator structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the semiconductor layer is fully oxidized to form insulation, then insulation coverage is improved, but stress in the channel region is relaxed

Engineering Contradiction:
Improveinsulation coverageVSAvoidstress in channel region
Core Design Contradiction:
ReliabilityVSStress or pressure

Solution Approach 1:

The semiconductor layer is divided into multiple portions: first portions are oxidized to form insulation, while a third portion is preserved to maintain stress. This segmentation allows different regions to serve different functions - insulation where needed and stress maintenance where transistors are formed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different portions of the semiconductor layer are treated differently: first portions are oxidized for insulation, while the third portion is kept unoxidized to maintain mechanical stress. This local differentiation enables simultaneous achievement of insulation coverage and stress preservation in critical regions.

Inventive Principle:
Principle #3Local quality

2Productivity

If stress is maintained in the channel region, then transistor performance is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvetransistor performanceVSAvoidmanufacturing process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Stress is introduced into the semiconductor layer before transistor fabrication through selective oxidation of surrounding portions. This preliminary stress generation simplifies subsequent manufacturing steps compared to introducing stress during or after transistor formation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The oxidized first portions act as intermediary structures that generate stress in the third portion through thermal or mechanical effects during oxidation. These intermediary oxidized regions indirectly provide the stress needed for transistor performance without directly interfering with the channel region.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Stress or pressure

If selective oxidation is performed to maintain stress, then stress integrity is improved, but manufacturing steps increase

Engineering Contradiction:
Improvestress integrityVSAvoidmanufacturing steps
Core Design Contradiction:
Stress or pressureVSDevice complexity

Solution Approach 1:

Multiple functions are merged into the selective oxidation process: it creates insulation in first portions, generates stress in the third portion, and defines transistor regions. This consolidation reduces the need for separate manufacturing steps compared to performing these functions independently.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method enhances the performance of constrained transistors by maintaining mechanical stresses, allowing for faster P-channel transistors and efficient integration of phase-change memory circuits, reducing the number of manufacturing steps and improving overall chip functionality.

Implementation Method 1

oxidizing first and second portions of the semiconductor layer to the insulator

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

generating stresses in a third portion of the semiconductor layer

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Implementation Method 3

doped emitter, base and collector semiconductor regions of the bipolar transistors are formed in first epitaxially grown semiconductor portions

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentEP4597561B1Electronic chip comprising stressed transistors
Publication Date: 2026.04.08 STMICROELECTRONICS INT NV
  • EP4597561B1 patent drawingFigure 1A~1B
  • EP4597561B1 patent drawingFigure 2A~2B
  • EP4597561B1 patent drawingFigure 3A~3B

AI summary

The present description relates to a method for manufacturing an electronic chip comprising the successive steps of: - providing a semiconductor layer (120) located on an insulator (130) covering a semiconductor substrate (110); - oxidizing first and second portions of the semiconductor layer down to the insulator, so as to form first oxidized portions (140) and second oxidized portions (150) on the insulator; - generating stresses (310) in a third portion (210) of the semiconductor layer not crossed by the first and second oxidized portions, the third portion extending continuously between the second oxidized portions (150); - forming cavities (410) extending at least to the semiconductor substrate through the second oxidized portions and the insulator; and - forming first field effect transistors in and on the third portion (210).