Stressed Semiconductor Substrate for MOSFET Scaling
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Solution Overview
Problem
The scaling of MOSFET channel length leads to significant short-channel effects, including reduced threshold voltage, increased power consumption, and reduced signal-to-noise ratio, which are challenging to mitigate with traditional manufacturing processes, especially in achieving fully depleted device structures.
Innovation Solution
A semiconductor device with a semiconductor substrate on an insulating layer, featuring source/drain regions and gates on opposite side surfaces, with an insulator embedded in the substrate to apply stress and increase the distance between gates and source/drain regions, reducing parasitic capacitance and resistance, and utilizing epitaxial source/drain regions to enhance carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length is scaled down to improve device density and integration, then productivity and device density are improved, but short-channel effects worsen causing reduced threshold voltage control and increased power consumption
Solution Approach 1:
The patent transitions from planar device architecture to a stereoscopic/vertical device structure where the channel extends in the vertical dimension rather than only laterally. This dimensional change allows the channel to achieve sufficient length for good threshold voltage control while maintaining small lateral footprint for high device density. The channel is formed as a vertical fin or ridge structure between source and drain regions, enabling the gate to control the channel from the sides rather than from above.
Solution Approach 2:
The patent employs SiGe source/drain regions with graded composition (varying Ge content) to create stress in the channel region. The SiGe material has different lattice constant than silicon, creating compressive or tensile stress that enhances carrier mobility and compensates for the reduced channel length effects. This composite material approach allows simultaneous achievement of high device density and good electrical performance.
2Reliability
If more dopant elements are doped into the channel to control short-channel effects, then threshold voltage control is improved, but carrier mobility deteriorates
Solution Approach 1:
The patent applies different doping strategies to different regions: the channel region is kept lightly doped or undoped to maintain high carrier mobility, while the source/drain regions are heavily doped to ensure good ohmic contact and low series resistance. The SiGe material is selectively placed in source/drain regions with graded Ge content to create stress in the channel without introducing excessive doping that would harm mobility.
Solution Approach 2:
The patent changes the material composition parameter by introducing SiGe with varying Ge content (from 0% to up to 70% Ge) in the source/drain regions. This compositional change creates lattice mismatch stress that enhances carrier mobility in the channel, providing an alternative mechanism to doping for controlling device characteristics while preserving high-speed performance.
3Productivity
If the gate oxide thickness is reduced to keep pace with gate width reduction, then device density is improved, but gate dielectric leaking current increases
Solution Approach 1:
The patent employs a gate dielectric stack comprising multiple layers with different properties: a thin interfacial oxide layer (2-5 nm) for good interface quality and low defect density, combined with a thicker high-k dielectric layer (such as HfO2, SrTiO3, or BaTiO3) for low leakage current. This composite dielectric structure enables the gate to achieve both thin effective thickness for high device density and low leakage current by utilizing the high dielectric constant of the upper layer.
4Speed
If the source/drain region width is increased to reduce resistance, then source/drain resistance is improved, but parasitic capacitance increases
Solution Approach 1:
The patent reduces source/drain resistance by extending the source/drain regions vertically in the third dimension rather than increasing their lateral width. The source and drain are formed as vertical structures that contact the channel along its length, providing a larger contact area and lower resistance without increasing the lateral footprint that would increase parasitic capacitance to neighboring devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces short-channel effects, parasitic capacitance, and source/drain resistance, while increasing carrier mobility by applying stress and optimizing the channel region structure, facilitating the transition to fully depleted device performance.
Implementation Method 1
an insulator embedded in the substrate to apply stress and increase the distance between gates and source/drain regions
Data Source
AI summary
A semiconductor device comprises: a semiconductor substrate located on an insulating layer; and an insulator located on the insulating layer and embedded in the semiconductor substrate, wherein the insulator applies stress therein to the semiconductor substrate. A method for forming a semiconductor device comprises: forming a semiconductor substrate on an insulating layer; forming a cavity within the semiconductor substrate so as to expose the insulating layer; forming an insulator in the cavity, wherein the insulator applies stress therein to the semiconductor substrate. It facilitates the reduction of the short channel effect, the resistance of source/drain regions and parasitic capacitance.