Stressed Transistor Memory Circuitry Using Dual Gate Oxide Process
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Solution Overview
Problem
Conventional memory element circuitry for integrated circuits requires a triple gate oxide process, which is complex and costly, whereas a dual gate oxide process would simplify manufacturing and reduce mask complexity.
Innovation Solution
The use of dual gate oxide complementary metal-oxide-semiconductor (CMOS) technology with stress-inducing layers during transistor fabrication, allowing for improved performance and reduced area requirements in memory element circuitry, enabling the integration of memory elements and pass transistors with optimized layouts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a triple gate oxide process is used to fabricate memory element circuitry with different transistor types (G, LP, I/O devices), then each transistor type can have optimized gate oxide thickness for its specific function, but the manufacturing process becomes complex and requires extra masks
Solution Approach 1:
The patent merges the fabrication process for different transistor types (G, LP, I/O devices) into a unified dual gate oxide process. Instead of using separate masks and processes for each transistor type, the invention combines them into two main process steps, reducing manufacturing complexity while maintaining the ability to provide different gate oxide thicknesses for different transistor types.
Solution Approach 2:
The patent applies local quality by providing different gate oxide thicknesses to different transistor types within the same integrated circuit. G devices receive one gate oxide thickness, LP devices receive a thicker gate oxide, and I/O devices receive the thickest gate oxide, with each thickness optimized for its specific functional requirements.
2Manufacturing precision
If a triple gate oxide process is used with separate masks for G, LP, and I/O gate oxides, then each transistor type can be precisely fabricated, but the number of masks and processing steps increases
Solution Approach 1:
The patent combines multiple fabrication steps into a dual gate oxide process that uses only two masks instead of three. The first mask defines regions for G and LP devices, while the second mask defines regions for I/O devices, eliminating the need for a separate third mask and reducing processing complexity.
Solution Approach 2:
The patent segments the fabrication process into two distinct gate oxide formation steps. The first step forms gate oxide for G and LP devices using a first mask, and the second step forms gate oxide for I/O devices using a second mask. This segmentation maintains manufacturing precision while reducing the total number of process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor performance, reduces manufacturing costs, and simplifies the processing by eliminating the need for extra masks, while maintaining high-speed operation and efficient data storage capabilities.
Implementation Method 1
Transistors associated with the memory element may be stressed with stress-inducing layers during fabrication
Data Source
AI summary
Integrated circuits with memory elements are provided. The memory elements may be arranged in a memory block. The memory block may include cross-coupled inverters that store data. The stored data may be used to program pass transistors. Transistors in the memory block may be stressed. Depending on the type of stress-inducing layer used, a tensile stress or a compressive stress may be built in into the transistors. Stressed transistors may help improve the routing speed of the memory block. Stressed transistors may be implemented using dual gate-oxide process.