Stressed Trench Isolation for Dual MOS Transistor Performance
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Solution Overview
Problem
Conventional shallow trench isolation (STI) technology enhances performance for one type of MOS transistor while degrading the other, limiting its application in CMOS devices.
Innovation Solution
A method involving the formation of tensile-stressed dielectric layers in trenches parallel to the channel length direction and low-stressed dielectric layers in trenches perpendicular to them, providing tensile stress in the channel width direction to improve the performance of both NMOS and PMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If tensile stress is applied to improve NMOS transistor performance, then NMOS driving current increases, but PMOS transistor performance degrades
Solution Approach 1:
The patent divides the trench isolation structure into two distinct sets: first trenches filled with tensile-stressed dielectric material and second trenches filled with compressive-stressed dielectric material. This segmentation allows different stress types to be applied to different transistor regions, enabling simultaneous optimization of both NMOS and PMOS performance rather than using a single uniform stress approach
Solution Approach 2:
The patent applies different stress characteristics to different spatial locations: tensile stress is localized in regions adjacent to NMOS transistors while compressive stress is localized in regions adjacent to PMOS transistors. This local quality approach ensures that each transistor type receives the optimal stress type for its operation, with the stress orientation and magnitude tailored to the specific transistor location
2Reliability
If conventional STI stress is applied to enhance one type of MOS transistor, then that transistor's performance improves, but the other type's performance deteriorates
Solution Approach 1:
The patent segments the isolation trenches into two categories with different stress properties, allowing independent optimization for each transistor type. The first trenches provide tensile stress for NMOS devices while the second trenches provide compressive stress for PMOS devices, ensuring both transistor types achieve reliable performance
Solution Approach 2:
The patent changes the stress parameter (from uniform to differential) by introducing two distinct stress states in the dielectric layers. The tensile-stressed and compressive-stressed dielectric materials create opposite stress directions, allowing the system to adapt the stress parameter to match the requirements of different transistor types
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the response speed and performance of MOS transistors, making it applicable to both PMOSFET and NMOSFET, and simplifies the semiconductor manufacturing process, especially at the 45 nm technical node and below, by ensuring consistent stress orientation for all MOS transistors.
Implementation Method 1
STI stress may induce strain of the channel, which may enhance the whole performance of the semiconductor device
Data Source
AI summary
A method for forming a semiconductor device with stressed trench isolation is provided, comprising: providing a silicon substrate (S11); forming at least two first trenches in parallel on the silicon substrate and forming a first dielectric layer which is under tensile stress in the first trenches (S12); forming at least two second trenches, which have an extension direction perpendicular to that of the first trenches, in parallel on the silicon substrate, and forming a second dielectric layer in the second trenches (S13); and after forming the first trenches, forming a gate stack on a part of the silicon substrate between two adjacent first trenches, wherein the channel length direction under the gate stack is parallel to the extension direction of the first trenches (S14). The present invention supply tensile stress in the channel width direction of a MOS transistor, so as to improve performance of PMOS and/or NMOS transistors.