Stressed Material Trenches for Semiconductor Warpage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor wafers experience warpage due to mismatched coefficients of thermal expansion (CTEs) and intrinsic stress, leading to bonding failures, delamination, and non-uniformity in processing, which decreases yield.
Innovation Solution
The method involves bonding two semiconductor substrates together, thinning one, etching trenches into its backside, and depositing a stressed material with intrinsic stress and a different CTE into these trenches to reduce warpage. This stressed material can be compressive or tensile, and its deposition can be modulated based on the expected warpage pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If materials with different CTEs are formed on the wafer, then functional integration is achieved, but warpage occurs due to CTE mismatch and intrinsic stress
Solution Approach 1:
The patent applies local quality by etching trenches at specific locations on the wafer backside and filling them with stressed material. This creates localized stress compensation zones that counteract the global warpage caused by CTE mismatch. The trenches are strategically positioned to address areas of maximum warpage curvature, allowing the wafer to maintain functional integration while restoring flatness through localized structural modification.
Solution Approach 2:
The patent changes physical parameters by introducing stressed material with specific stress characteristics into the trenches. The stressed material is deposited with controlled tensile or compressive stress to counterbalance the warpage-inducing stresses from CTE mismatch. By adjusting the stress parameters of the filling material and the trench geometry, the wafer's overall stress state is modified to achieve flatness while preserving the functional material stack.
2Productivity
If wafer bonding is performed, then device integration is achieved, but bonding failures occur due to warpage at the bonding interface
Solution Approach 1:
The patent applies preliminary action by performing wafer thinning and trench filling with stressed material before the bonding process. This pre-treatment compensates for warpage that would otherwise occur during bonding, ensuring that the wafer maintains adequate flatness when brought into contact with the bonding partner. The stressed material is deposited in advance to counteract the thermal and mechanical stresses that will be experienced during subsequent bonding operations.
Solution Approach 2:
The patent applies preliminary anti-action by introducing stressed material that generates counter-stresses to the warpage forces. The stressed material in the trenches creates opposing stress fields that neutralize the warpage-inducing stresses from CTE mismatch before bonding occurs. This pre-applied counter-action prevents bonding interface failures by ensuring the wafer remains sufficiently flat during the critical bonding process.
3Adaptability or versatility
If further processing is performed after bonding, then device functionality is enhanced, but polishing and thinning uniformity deteriorate due to warpage
Solution Approach 1:
The patent applies local quality by creating trenches with stressed material at specific locations on the wafer backside. These localized stress compensation zones counteract warpage in the regions most critical for subsequent polishing and thinning operations. By strategically positioning the trenches, the patent ensures that areas requiring high precision processing maintain adequate flatness, enabling enhanced device functionality through subsequent processing steps.
Solution Approach 2:
The patent changes the stress parameters of the wafer structure by introducing stressed material into the trenches. This modifies the wafer's mechanical properties and stress distribution, improving flatness for subsequent polishing and thinning operations. The controlled stress in the filling material compensates for warpage, allowing precise control of material removal rates during CMP and thinning while maintaining uniformity across the wafer surface.
4Length of moving object
If wafer thinning is performed, then device miniaturization is achieved, but warpage increases due to reduced substrate stiffness
Solution Approach 1:
The patent applies local quality by etching trenches and filling them with stressed material at specific locations on the thinned wafer backside. This creates localized reinforcement zones that counteract the warpage induced by thinning. The trenches are positioned to address areas of maximum curvature, providing local stress compensation that restores flatness to the thinned wafer without requiring reversal to thicker dimensions.
Solution Approach 2:
The patent changes the stress parameters of the thinned wafer by introducing stressed material into the trenches. The stressed material compensates for the stress imbalances created by thinning, counteracting the warpage that occurs when substrate stiffness is reduced. By adjusting the stress and geometry of the trench filling, the patent restores adequate flatness to thinned wafers, enabling device miniaturization while maintaining processing quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The technique effectively reduces warpage in semiconductor substrates, preventing bonding failures and ensuring uniformity in processing, thereby enhancing yield and reducing issues like delamination and photolithography misalignment.
Implementation Method 1
A first stressed material is deposited into the first trench
Implementation Method 2
Warpage of the wafer can occur because of different coefficient of thermal expansions (CTEs) and intrinsic stress of materials formed on the wafer, such as during thermal cycling
Data Source
AI summary
Examples described herein provide a method for reducing warpage when stacking semiconductor substrates. In an example, a first substrate is bonded with a second substrate to form a stack. The first substrate comprises a first semiconductor substrate, and the second substrate comprises a second semiconductor substrate. The second semiconductor substrate is thinned, and a first trench is etched into a backside of the thinned second semiconductor substrate. A first stressed material is deposited into the first trench.