Semiconductor Stressor Buffer Region for Uniform SiGe Epitaxy
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in achieving uniform and efficient epitaxial growth of stressor regions, such as SiGe, within the tight geometries of integrated circuits, which affects carrier mobility and device performance, particularly due to issues with facet plane formation near shallow trench isolation structures.
Innovation Solution
The method involves forming a buffer region with a width greater than 1 nanometer between the stressor and the isolation feature, allowing for uniform epitaxy growth of SiGe and enabling accurate control of electrical performance by maintaining the same material continuity between the stressor and the substrate, thereby enhancing carrier mobility and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If epitaxial growth is performed in tight geometries near shallow trench isolation structures, then device integration density is improved, but uniformity of SiGe growth deteriorates due to facet plane formation
Solution Approach 1:
A buffer region consisting of silicon material is introduced as an intermediary between the stressor (SiGe) and the shallow trench isolation structure. This buffer region mediates the interaction between the stressor and STI, preventing direct contact that causes facet plane formation. The buffer region allows the stressor to be positioned close to the STI for high integration density while maintaining uniform SiGe growth by eliminating the harmful geometric constraints at the stressor-STI interface.
2Area of stationary object
If stressor is positioned close to shallow trench isolation structure, then area utilization is improved, but leakage current increases due to facet plane issues
Solution Approach 1:
The silicon buffer region serves as a mediator that enables the stressor to be positioned close to the STI structure for maximum area utilization while preventing the formation of facet planes that generate leakage current. The buffer region electrically isolates the stressor from the STI structure, eliminating the harmful electrical effects while maintaining spatial efficiency.
3Manufacturing precision
If buffer region with width greater than 1 nanometer is formed, then uniformity of epitaxial growth is improved, but manufacturing complexity increases
Solution Approach 1:
The invention specifies a minimum buffer region width of greater than 1 nanometer to ensure uniform epitaxial growth of SiGe. This parameter change (buffer width threshold) provides a clear manufacturing criterion that balances growth uniformity with process simplicity. By establishing a specific dimensional parameter, the invention transforms a complex growth control problem into a straightforward geometric constraint that can be easily implemented and verified in manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the uniformity of SiGe growth, reduces leakage current, and increases yield by moderating facet plane issues near STI structures, leading to better electrical performance and contact formation accuracy in integrated circuits.
Implementation Method 1
allowing for uniform epitaxy growth of SiGe
Data Source
AI summary
A semiconductor structure includes a substrate, a shallow trench isolation (STI) structure embedded in the substrate, a stressor embedded in the substrate, and a conductive plug over and electrically coupled with the stressor. A same-material region is sandwiched by the STI structure and an entire sidewall of the stressor, and the same-material region is a continuous portion of the substrate.