Stressor Layer Strain Engineering for SRAM Leakage Control
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Solution Overview
Problem
Ultra-low voltage SRAMs below 40 nanometers face higher standby leakage current due to the omission of the P-type lightly doped drain (PLDD) mask, leading to excessive electrical performance of PMOS pull-up transistors.
Innovation Solution
A stressor layer with tensile stress is deposited over NMOS and PMOS transistors, inducing compressive strain during an annealing process, which enhances NMOS performance while intentionally degrading PMOS performance to normalize standby leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the P-type lightly doped drain (PLDD) mask is omitted in ultra-low voltage SRAM manufacturing, then device performance is improved, but standby leakage current increases excessively
Solution Approach 1:
The patent applies different stress conditions to different transistor types: tensile stress is applied to NMOS transistors to enhance their performance, while compressive stress is applied to PMOS transistors to reduce their drive current and lower standby leakage. This localized differentiation of stress quality allows simultaneous optimization of performance and leakage without requiring the PLDD mask
Solution Approach 2:
The patent changes the stress parameter (tensile vs. compressive) applied to different transistor channels. By controlling the stressor layer configuration and annealing conditions, the patent modifies the physical state of the channel regions to achieve desired electrical characteristics - enhanced mobility for NMOS and reduced leakage for PMOS
2Speed
If tensile stress is applied to NMOS transistors, then carrier mobility is enhanced, but device complexity increases due to stressor layer deposition and annealing processes
Solution Approach 1:
The stressor layer deposition and annealing process serves multiple functions simultaneously: it enhances NMOS performance through tensile stress, reduces PMOS leakage through compressive stress, and recrystallizes the polysilicon gates. By combining these functions into a single process sequence, the patent minimizes additional process complexity while achieving multiple performance improvements
3Object-generated harmful factors
If compressive stress is applied to PMOS transistors, then standby leakage current is reduced, but transistor drive current decreases
Solution Approach 1:
The patent applies compressive stress locally and selectively to PMOS transistor channels to reduce their drive current and lower standby leakage. This localized stress application is achieved through specific stressor layer configurations and annealing conditions that target PMOS devices without significantly affecting NMOS performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces the excessive performance of PMOS pull-up transistors, thereby restoring standby leakage current to a normal range in SRAMs.
Implementation Method 1
A stressor layer with tensile stress is deposited over NMOS and PMOS transistors, inducing compressive strain during an annealing process
Implementation Method 2
inducing compressive strain during an annealing process, which enhances NMOS performance while intentionally degrading PMOS performance
Implementation Method 3
The first transistor and the second transistor are subjected to an annealing process to recrystallize the first gate and the second gate under the influence of the stressor layer
Implementation Method 4
subjected to an annealing process to recrystallize the first gate and the second gate
Data Source
AI summary
A method of forming semiconductor device is disclosed. A substrate having a logic circuit region and a memory cell region is provided. A first transistor with a first gate is formed in the logic circuit region and a second transistor with a second gate is formed in the memory cell region. A stressor layer is deposited to cover the first transistor in the logic circuit region and the second transistor in the memory cell region. The first transistor and the second transistor are subjected to an annealing process under the influence of the stressor layer to recrystallize the first gate and the second gate.