Arithmetic Processing Apparatus Stride Access Detection
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Solution Overview
Problem
Arithmetic processing units face inefficiencies in memory access speed due to the need to decompose single instructions into multiple scalar access instructions for non-stride memory access patterns, which reduces overall memory access speed.
Innovation Solution
An arithmetic processing apparatus that includes a processor capable of detecting whether memory access intervals are the same or not, allowing it to decode instructions accordingly and perform memory access efficiently, utilizing a history table and stride access detection circuit to optimize memory access by treating stride access instructions as single instructions and non-stride access instructions as multiple scalar instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory access instructions are decomposed into multiple scalar access instructions for non-stride patterns, then memory access flexibility is improved, but memory access speed deteriorates
Solution Approach 1:
The system dynamically determines whether to treat a memory access instruction as a single instruction or decompose it into multiple scalar instructions based on real-time detection of address interval patterns. The stride access detection circuit continuously monitors address intervals and controls the instruction decode unit to switch between single-instruction execution and multi-instruction decomposition, optimizing performance for different access patterns without sacrificing flexibility
Solution Approach 2:
The system changes the operational parameter of the memory access instruction based on the detected access pattern. When uniform address intervals are detected, the instruction is executed as a single operation with optimized parameters. When non-uniform intervals are detected, the instruction parameter changes to decompose into multiple scalar operations, maintaining adaptability while improving speed for stride patterns
2Speed
If all memory access instructions are treated as single instructions, then memory access speed is improved for stride patterns, but processing accuracy deteriorates for non-stride patterns
Solution Approach 1:
The stride access detection circuit provides feedback about address interval patterns to the instruction decode unit. This feedback mechanism allows the system to verify whether address intervals are uniform before executing as a single instruction. If the feedback indicates non-uniform intervals, the system switches to multi-instruction decomposition, ensuring processing accuracy is maintained for non-stride patterns while enabling speed optimization for stride patterns
3Manufacturing precision
If memory access instructions are decomposed into multiple scalar instructions, then processing accuracy is improved for non-stride patterns, but memory access speed deteriorates
Solution Approach 1:
The system segments memory access instructions into multiple scalar instructions only when necessary, based on detection of non-uniform address intervals. For stride patterns with uniform intervals, the instruction remains unsegmented and executes as a single operation, maintaining high productivity. This selective segmentation approach ensures processing accuracy for complex access patterns while preserving speed for simple stride patterns
Data Source
AI summary
An arithmetic processing apparatus includes: a memory; and a processor coupled to the memory, wherein the processor: detects whether intervals of a plurality of addresses to be accessed by a memory access instruction that performs memory access to the plurality of addresses by a single instruction are all the same; decodes the memory access instruction as the single instruction when detecting that the intervals are all the same; decodes the memory access instruction as a plurality of instructions when detecting that the intervals are not all the same; and performs the memory access in accordance with the single instruction or the plurality of instructions.