Strideshift Instruction for Vector Register Bit Transposition
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Solution Overview
Problem
Conventional techniques for determining the maximum and minimum values in a vector are inefficient, requiring multiple instructions and temporal registers, and can have high latency due to the need for square all-to-all comparisons and subsequent processing steps.
Innovation Solution
The introduction of a strideshift instruction that transposes the result of a square all-to-all comparison instruction, allowing for the determination of both maximum and minimum values in a vector using a single square all-to-all comparison followed by a strideshift operation and comparison with a pre-defined matrix.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional pairwise comparison techniques are used to determine maximum and minimum values in a vector, then the operation can be performed using standard instructions, but the number of instructions required increases to 16 and multiple temporal registers are needed
Solution Approach 1:
The patent segments the comparison operation into two distinct phases: first performing a square all-to-all comparison to generate a comparison matrix, then transposing this matrix to simultaneously extract both maximum and minimum values. This segmentation allows the complex operation to be completed in fewer instructions by breaking it into manageable stages that can be executed efficiently.
Solution Approach 2:
The patent transforms the comparison operation from a sequential element-by-element process into a two-dimensional matrix operation. By representing comparisons as a matrix where rows and columns correspond to vector elements, the system can perform multiple comparisons simultaneously and extract both max and min values through matrix transposition, reducing the total instruction count from 16 to 6.
2Productivity
If square all-to-all comparison instructions are used to determine maximum values, then all comparisons can be obtained in a single instruction, but the instruction has high latency and may turn into a long sequence of micro-instructions
Solution Approach 1:
The patent performs the square all-to-all comparison as a preliminary action that generates a complete comparison matrix in one instruction. Although this instruction has high latency, the result is reused for both maximum and minimum value determination. By preparing the comparison matrix upfront, subsequent operations can proceed efficiently without repeating the expensive comparison operation.
Solution Approach 2:
The patent merges the determination of maximum and minimum values into a single workflow by reusing the comparison matrix. Instead of performing separate comparison operations, the transposed matrix enables both max and min extraction simultaneously, effectively combining two operations into one instruction sequence and reducing overall latency.
3Productivity
If multiple temporal registers are used to store intermediate results in conventional techniques, then the computation can proceed in stages, but the register usage increases and efficiency decreases
Solution Approach 1:
The comparison matrix serves multiple functions: it stores the results of all pairwise comparisons, enables extraction of maximum values, and after transposition enables extraction of minimum values. This multi-functionality eliminates the need for separate temporary registers for different comparison stages, as the same matrix structure is reused throughout the computation process.
Solution Approach 2:
The patent discards the need for multiple temporary registers by recovering and reusing the comparison matrix after transposition. The same data structure that captured comparison results is transformed and reused for the second extraction phase, maximizing resource utilization and minimizing the total number of registers required.
Data Source
AI summary
A processor includes a decode circuit to decode an instruction into a decoded instruction and an execution circuit to execute the decoded instruction to access a first bit of a first input vector located at a bit position indicated by an element of a second input vector, stride over bits of the first input vector using a stride to access bits of the first input vector that are located at a strided bit position with respect to the first bit of the first input vector, and store the first bit of the first input vector and the bits of the first input vector that are located at a strided bit position with respect to the first bit of the first input vector as consecutive bits in a destination vector.