String-Based Erase Inhibit for 3D NAND Memory
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Solution Overview
Problem
In 3D stacked non-volatile memory devices, fast-erasing memory cells can undergo over-erase during conventional erase operations, leading to degradation due to excessive holes accumulating in the tunneling path, as existing methods do not effectively inhibit the erase process for cells that have already reached the erase state.
Innovation Solution
A string-based erase inhibit scheme is implemented, where memory strings that pass the erase-verify test are inhibited by ramping up the voltage applied to their SGD or SGS transistors before the bit line or source line, ensuring complete cutoff of VERA bias and preventing further erase, thereby avoiding over-erase and improving data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional erase operations are performed on all memory strings without inhibition, then erase completeness is improved, but over-erase degradation occurs due to excessive holes accumulating in the tunneling path
Solution Approach 1:
The patent applies preliminary action by performing an erase-verify test before completing the erase operation on each memory string. The control circuit determines whether a memory string has reached the erase state after applying erase voltage, and inhibits further erase operations on strings that have already been successfully erased. This preliminary verification prevents excessive hole accumulation in the tunneling path while ensuring complete erasure of all memory cells.
Solution Approach 2:
The patent implements feedback through the erase-verify mechanism where the state of memory strings is continuously monitored during the erase operation. The control circuit receives feedback from the verify test results and dynamically adjusts the erase operation by inhibiting further erasure on strings that have reached the target state. This feedback loop ensures that erase operations are stopped at the optimal point, preventing over-erase degradation while maintaining erase completeness.
2Productivity
If erase voltage is applied continuously to all memory strings, then erase speed is improved, but energy consumption increases and over-erase occurs
Solution Approach 1:
The patent applies preliminary action by performing an erase-verify test before completing the erase operation on each memory string. The control circuit determines whether a memory string has reached the erase state after applying erase voltage, and inhibits further erase operations on strings that have already been successfully erased. This preliminary verification prevents excessive hole accumulation in the tunneling path while ensuring complete erasure of all memory cells.
Solution Approach 2:
The patent applies partial action by selectively continuing or inhibiting erase operations on individual memory strings based on their erase state. Instead of applying erase voltage uniformly to all memory strings throughout the entire erase operation, the control circuit applies erase voltage only to strings that have not yet reached the target state, as determined by the erase-verify test. This partial application of erase action reduces unnecessary energy consumption and prevents over-erase on already-completed strings.
3Productivity
If erase operations are performed on all memory strings simultaneously, then processing efficiency is improved, but interference from neighbor word-lines increases
Solution Approach 1:
The patent applies local quality by treating different memory strings differently based on their individual erase states. The control circuit selectively continues or inhibits erase operations on specific memory strings based on the results of erase-verify tests performed on each string. This localized approach allows simultaneous processing of multiple strings while applying erase voltage only where needed, reducing interference from neighbor word-lines and improving overall processing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents over-erase of memory cells that have reached the erase state quickly, reducing degradation and enhancing memory cell reliability by maintaining a well-controlled erase state and minimizing disturb effects from neighbor word-lines.
Implementation Method 1
inhibiting the at least one memory string for erase including ramping up, to an erase voltage, of a voltage applied to a gate of a SGD transistor of the at least one memory string
Data Source
AI summary
A non-volatile memory device, described herein, comprises: a plurality of memory strings and at least one control circuit in communication with the non-volatile memory cell array. The at least one control circuit is configured to perform, for the plurality of memory strings, one erase-verify iteration in an erase operation including determining whether at least one memory string of the plurality of memory strings passes an erase-verify test. The at least one control circuit is configured to, if the at least one memory string passes the erase-verify test, inhibit the at least one memory string for erase including ramping up, to an erase voltage, of a voltage applied to a gate of a SGD transistor of the at least one memory string and to perform a next erase-verify iteration in the erase operation for remaining memory strings of the plurality of memory strings other than the at least one memory string.