String Selection Line Biasing for Faster Vertical Memory Reads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Vertical memory devices with channel holes experience variations in memory cell characteristics due to distance from isolation regions, leading to increased operation times.
Innovation Solution
Applying a prepulse voltage followed by a negative bias voltage to unselected string selection lines, with varying levels based on the region's proximity to word lines, to reduce resistance differences and enhance operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical memory devices use channel holes stacked vertically to increase capacity, then storage density is improved, but characteristics of memory cells vary with distance from isolation region leading to increased operation time
Solution Approach 1:
The patent applies different voltage levels to different string selection lines based on their spatial location. Specifically, string selection lines in first regions (closer to isolation regions) receive a first voltage level, while string selection lines in second regions (farther from isolation regions) receive a second voltage level. This local differentiation compensates for the varying characteristics of memory cells at different distances from isolation regions, thereby reducing operation time variations across the vertical channel structures.
2Device complexity
If uniform voltage is applied to all string selection lines, then device complexity is reduced, but resistance differences between channels cause varying operation times
Solution Approach 1:
The patent implements local quality by dividing the memory device into multiple regions based on distance from isolation regions, and applying different voltage levels to string selection lines in different regions. This approach addresses the resistance differences and characteristic variations in different spatial locations without requiring complex individual control of each string selection line, thus balancing device complexity with operation time uniformity.
3Reliability
If prepulse operation is performed on all string selection lines, then read operation reliability is improved, but operation time increases due to varying recovery times
Solution Approach 1:
The patent changes the voltage parameter applied to string selection lines based on their spatial location. By applying a first voltage level to string selection lines in first regions and a second voltage level to string selection lines in second regions, the patent optimizes the prepulse operation timing for each region, thereby reducing overall prepulse operation time while maintaining read operation reliability.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Provided is a memory device. The memory device includes a memory cell array including a plurality of memory cells and a plurality of string selection lines, a negative charge pump configured to generate a bias voltage of a negative level, to be applied to at least one of the plurality of string selection lines, and a control logic circuit configured to apply, for a first period, a prepulse voltage to at least one unselected string selection line among the plurality of string selection lines excluding a selected string selection line to which a memory cell selected from among the plurality of memory cells is connected and thereafter apply the bias voltage to the at least one unselected string selection line so as to perform a read operation on the selected memory cell.