Strip Gate Contact with High-K Dielectric for Semiconductor Devices
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Solution Overview
Problem
The miniaturization of integrated circuits (ICs) has led to challenges in designing semiconductor devices that require increased design flexibility for effective electrical coupling of gate and source/drain contacts without impacting the landing margin of source/drain contacts, particularly in ensuring reliable contact areas and minimizing electrical interference.
Innovation Solution
The semiconductor device incorporates gate contacts and source/drain contacts with conductive plugs surrounded by dielectric materials having a higher dielectric constant than the surrounding inter-layer dielectric, arranged in a strip shape to enhance contact areas and electrical isolation, while maintaining the integrity of the source/drain contact landing margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If gate contacts and source/drain contacts are arranged in conventional configurations, then manufacturing is simpler, but design flexibility for effective electrical coupling is reduced
Solution Approach 1:
A dielectric material with a higher dielectric constant than the surrounding inter-layer dielectric is introduced as an intermediary between the conductive plug and the gate contact. This intermediary dielectric layer enables effective electrical coupling while maintaining design flexibility, as the higher dielectric constant material enhances the electrical field interaction without requiring complex structural modifications to the contact arrangement itself.
2Reliability
If contact areas are increased to improve electrical coupling, then electrical interference increases, but if contact areas are reduced to minimize interference, then coupling effectiveness decreases
Solution Approach 1:
The dielectric material surrounding the conductive plug is configured with spatially varying properties: in the region adjacent to the gate contact, the dielectric has a higher dielectric constant to enhance electrical coupling effectiveness, while in other regions it maintains standard dielectric properties to minimize electrical interference. This local differentiation of dielectric quality allows the structure to simultaneously achieve effective coupling where needed while controlling interference in other areas.
3Reliability
If source/drain contact landing margins are reduced to increase device density, then contact reliability decreases, but if landing margins are increased to improve reliability, then device density decreases
Solution Approach 1:
The higher dielectric constant material acts as an intermediary that enhances the electrical field distribution around the conductive plug, effectively improving the electrical coupling and reliability of the source/drain contacts. This allows the landing margins to be reduced without compromising reliability, as the enhanced dielectric properties compensate for the reduced physical margin, thereby enabling increased device density within the same area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the design flexibility and electrical coupling of gate and source/drain contacts, ensuring increased contact areas and reduced electrical interference, thereby enhancing the performance and reliability of the semiconductor device.
Implementation Method 1
conductive plugs surrounded by dielectric materials having a higher dielectric constant than the surrounding inter-layer dielectric
Data Source
AI summary
A semiconductor device includes a first semiconductor structure, a second semiconductor structure, a gate, and a gate contact. The first semiconductor structure and a second semiconductor structure are of different types. Each of the first semiconductor structure and the second semiconductor structure has a source, a drain and a channel region extends between the source and the drain. The gate extends across the channel regions of the first semiconductor structure and the second semiconductor structure. The gate contact directly is on the gate. The gate contact has a strip shape of which a ratio of a length to a width is at least 2 and includes a gate conductive plug and a gate contact dielectric. The gate conductive plug is directly in contact with the gate. The gate contact dielectric surrounds side surfaces of the gate conductive plug and having a frame shape.