Strip-Shaped Via Structure for Crack-Resistant Semiconductor Interconnects
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Solution Overview
Problem
The challenge of forming reliable semiconductor devices at smaller sizes is exacerbated by the increasing complexity and difficulty of fabrication processes as feature sizes continue to decrease, leading to issues with crack formation and reliability in conductive structures.
Innovation Solution
The formation of conductive via structures with a strip shape and increased contact area with conductive pillars and lines, using specific fabrication processes such as photolithography and sputtering, to enhance adhesion and prevent cracks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency is improved and costs are lowered, but fabrication process difficulty increases and reliability deteriorates due to crack formation
Solution Approach 1:
The patent applies local quality by creating a conductive via structure with non-uniform width, where the width varies along the vertical direction. The via structure has a wider upper portion and a narrower lower portion, allowing different regions to serve different functions: the wider upper portion provides increased contact area with the conductive line for better electrical connection, while the narrower lower portion fits within the constrained geometry of smaller feature sizes. This local variation in geometry resolves the contradiction by maintaining reliability through optimized local contact areas while overall device dimensions are scaled down for improved productivity.
2Productivity
If feature sizes are decreased to increase functional density, then production efficiency is improved and costs are lowered, but fabrication process complexity increases
Solution Approach 1:
The patent resolves the contradiction by moving the complexity management to another dimension - the vertical dimension. Instead of increasing lateral complexity to achieve the non-uniform via shape, the patent uses vertical dimensionality by forming the via structure with varying width at different heights. This is achieved through selective etching processes that create the tapered or stepped profile, allowing the complex geometry to be realized through vertical process control rather than lateral fabrication steps, thus managing complexity while maintaining scaled-down feature sizes for improved productivity.
3Reliability
If contact area between conductive elements is increased to prevent cracks, then reliability is improved, but device geometry constraints are violated at smaller feature sizes
Solution Approach 1:
The patent applies the nesting principle by placing the conductive via structure within the hole formed in the insulating layer, and further nesting the conductive line within the upper portion of the via structure. The via structure acts as an intermediary element that is nested between the conductive pillar (below) and the conductive line (above). This nested arrangement allows the contact area to be increased vertically through the via's extended height and varied width, rather than requiring increased lateral contact area that would violate the constrained device geometry at smaller feature sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability of semiconductor devices by increasing the contact area between conductive elements, thereby reducing crack formation and enhancing the structural integrity of the semiconductor device structure.
Implementation Method 1
using specific fabrication processes such as photolithography and sputtering
Implementation Method 2
using specific fabrication processes such as photolithography and sputtering
Data Source
AI summary
A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a first insulating layer, and a conductive pillar over the substrate. The conductive pillar is embedded in the first insulating layer, and a top surface of the conductive pillar is exposed by the first insulating layer. The method includes forming a second insulating layer over the first insulating layer and the conductive pillar. The second insulating layer has a hole over the top surface of the conductive pillar. The method includes forming a conductive via structure in the hole and a conductive line over the conductive via structure and the second insulating layer. The conductive via structure has a first strip shape in a first top view of the conductive via structure.