Semiconductor Device With Stripe-Shaped Gate Electrodes
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Solution Overview
Problem
The existing semiconductor device structures, such as power MOSFETs and IGBTs, face limitations in reducing on-resistance while maintaining high-speed operation due to constraints in lithography and mask alignment, which restrict the refinement of pattern spacing and gate width per unit area.
Innovation Solution
The semiconductor device features stripe-shaped source regions and gate electrodes with partially exposed contact holes, allowing for reduced spacing between gate electrodes and increased gate width without increasing gate resistance, achieved through a method of forming insulating films with strategically placed contact holes and silicide layers for reduced resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the spacing between gate electrodes is reduced to increase gate width per unit area, then on-resistance is reduced, but lithography and mask alignment limitations prevent further pattern refinement
Solution Approach 1:
The gate electrode structure is segmented into multiple fingers that extend in the longitudinal direction. This segmentation allows the gate width to be increased by adding more fingers rather than widening individual gates, thereby maintaining manageable spacing that can be manufactured with current lithography capabilities while still achieving increased gate width per unit area.
Solution Approach 2:
Instead of increasing gate width by reducing spacing in the lateral direction (which is limited by lithography), the invention extends the gate electrodes in the longitudinal direction. This dimensional transition allows gate width to be increased without being constrained by minimum spacing requirements, effectively bypassing the lithography limitation.
2Manufacturing precision
If the gate electrode width is reduced to increase the number of gates per unit area, then gate width per unit area increases, but gate resistance increases and high-speed operation is hampered
Solution Approach 1:
The gate electrode is divided into multiple narrow fingers that are distributed across the device area. While each individual finger is narrow, the cumulative gate width across all fingers is large. This segmentation allows maintaining acceptable gate resistance in each finger while achieving high total gate width per unit area through the distributed arrangement of multiple fingers.
Solution Approach 2:
The invention transitions from widening gates in the lateral direction to extending gates in the longitudinal direction. By making gates longer rather than wider, the design achieves increased gate width per unit area without reducing gate electrode cross-sectional area, thereby maintaining low gate resistance while improving the gate width to area ratio.
3Reliability
If contact holes are formed over the entire length of source regions, then source electrode connection is ensured, but spacing between gate electrodes is limited by minimum contact hole size and mask alignment tolerance
Solution Approach 1:
The invention extracts the contact hole formation requirement from the entire length of the source region and concentrates it only at the longitudinal ends. This selective placement ensures adequate source electrode connection at critical points while removing the constraint of continuous contact hole formation, thereby enabling reduced spacing between gate electrodes in the regions between contact holes.
Solution Approach 2:
Instead of uniformly forming contact holes along the entire source region, the invention applies contact holes only at specific locations (longitudinal ends) where connection is most critical. This local quality approach ensures reliable electrical connection where needed while allowing tighter gate spacing in other regions, optimizing both connection reliability and space utilization.
Data Source
AI summary
The semiconductor device includes a semiconductor substrate, a plurality of source regions formed in a stripe shape on the semiconductor substrate, a plurality of gate electrodes formed in a stripe shape between a plurality of the stripe shaped source regions on the semiconductor substrate, an insulating film for covering the source regions and the gate electrodes, the insulating film including a contact hole for partly exposing the source regions in a part of a predetermined region with respect to a longitudinal direction of the source regions; and a source electrode formed on the insulating film and electrically connected to the source region via the contact hole.