Semiconductor Chip Stripe Interconnection for Thin Multi-Chip Packages
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional multi-chip packages face issues with bonding wire defects and increased package thickness due to long distances between pads, leading to undesirable wire bending and unreliable connections.
Innovation Solution
The solution involves forming interconnection patterns as stripes on the surface of semiconductor chips, with pads connected to these patterns through vias, allowing for direct electrical connections between chips without the need for bonding wires, enabling pad-to-pad, interconnection pattern-to-interconnection pattern, or interconnection pattern-to-pad contacts, which reduces package thickness and prevents wire-related defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding wires are used to connect pads between chips and substrate, then electrical connections can be established, but the long distance between pads causes wire bending, unreliable connections, and potential contact with non-designated portions
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional direct pad-to-pad contact through chip stacking. The bonding pads are positioned on opposing surfaces of adjacent chips, enabling vertical electrical connection that eliminates long lateral wire paths and their associated reliability issues.
Solution Approach 2:
The patent eliminates the bonding wire intermediary by establishing direct electrical contact between bonding pads on adjacent chips. This removes the wire-related problems of bending, instability, and unintended contacts while maintaining electrical connectivity.
2Reliability
If an interface chip is used to establish electrical connections between chips and substrate, then connections can be made, but the package thickness increases excessively
Solution Approach 1:
The patent removes the interface chip intermediary layer by enabling direct pad-to-pad contact between stacked chips. This eliminates the additional thickness contributed by the interface chip while maintaining reliable electrical connections through precise pad alignment on opposing chip surfaces.
Solution Approach 2:
The patent achieves electrical connection in the vertical dimension through direct pad contact between stacked chips, eliminating the need for lateral expansion or additional intermediate layers that would increase package thickness.
3Reliability
If pads are connected to interconnection layer of interface board by bonding wires, then electrical connections are established, but the interface board size becomes greater than semiconductor chip size
Solution Approach 1:
The patent eliminates the interface board by establishing direct electrical contact between bonding pads on adjacent chips. This removes the need for a larger interface board structure while maintaining reliable electrical connectivity through precise pad alignment in the vertical stacking direction.
Data Source
AI summary
There is provided a semiconductor chip and a multi-chip package. Each semiconductor chip includes a plurality of pads formed on a first surface thereof and electrically connected to an integrated circuit, and interconnection patterns formed as stripes on a second surface of the semiconductor chip. The interconnection patterns are formed by transferring a part of the basic layout configured with a pattern of stripes extending from a center portion to an edge portion, wherein the pads are electrically connected to the interconnection patterns.