Hierarchical Stripe Lock Cache Table for Storage I/O
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current storage devices with dual SPs face performance bottlenecks due to high message transmission frequency in active-active architectures, particularly in stripe lock processing, which leads to increased odds of IO operation collisions and reduced processing speed.
Innovation Solution
The implementation of a hierarchical stripe lock cache table system, where cache tables are dynamically generated based on IO request frequency, allowing for a finer granularity and reducing the need for frequent CMI message transmissions by adjusting cache slot sizes and reclaiming unnecessary cache tables.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a common message infrastructure is used for dual SPs in active-active architecture, then failover reliability is improved, but message transmission frequency increases causing performance degradation
Solution Approach 1:
The patent segments the cache table into multiple cache slots, each slot independently caching permission states for specific storage address ranges. This segmentation allows the system to check multiple slots in parallel, reducing the frequency of CMI message transmissions needed for permission verification, thereby improving processing speed while maintaining failover reliability.
Solution Approach 2:
The patent implements preliminary action by pre-caching permission states of the second SP in the cache table before actual IO operations occur. When an IO request arrives, the first SP can quickly check the cached permission states locally without immediately contacting the second SP via CMI messages, reducing message transmission frequency and improving processing speed while ensuring reliable failover.
2Productivity
If cache table size is increased to reduce message transmission, then processing efficiency is improved, but storage occupancy increases
Solution Approach 1:
The patent divides the cache table into multiple cache slots, each storing permission states for specific storage address ranges. This segmentation allows the system to use only the necessary portion of cache storage at any given time, reducing overall storage occupancy while maintaining high processing efficiency through selective cache slot utilization.
Solution Approach 2:
The patent applies local quality by making each cache slot specialize in caching permission states for specific storage address ranges. This allows the cache structure to be optimized locally for each slot's specific usage pattern, improving processing efficiency for targeted operations while minimizing the total storage occupancy required across the entire cache table.
Data Source
AI summary
A method, computer program product, and apparatus for processing an input/output IO operation request by maintaining a first chain table and a first cache table for each of the plurality of storage array groups, the method, computer program product, and apparatus including generating a second cache table comprising a second plurality of cache slots for the cache slot in the first plurality of cache slots, corresponding to a specific storage address range for which a number of times of the IO operation requests exceeds a first predetermined threshold; and processing the IO operation request received by the first processor based at least on the first chain table and the first cache table and/or the second cache table.