Stripe-Based Memory Write Performance via Concurrent Data Placement

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Solution Overview

Problem

Existing stripe-based memory systems face inefficiencies in updating data without reading or copying original data, leading to increased operational overhead and potential errors, particularly in handling uncorrectable errors within a stripe.

Innovation Solution

The non-volatile memory control circuitry is configured to write unrelated data concurrently with updated data in a second stripe, detect errors, and remove the erroneous portion of the stripe, allowing the system to operate without the removed portion, thereby reducing overhead and maintaining data integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If original data is read and copied during stripe updates, then data integrity is maintained, but operational overhead increases and performance deteriorates

Engineering Contradiction:
Improvewrite performanceVSAvoidoperational overhead
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system performs preliminary actions by pre-positioning unrelated data in buffers before stripe update operations. When a stripe needs to be updated, the unrelated data is already prepared and can be written concurrently with the updated data, eliminating the need to read and copy original data first. This preliminary preparation reduces operational overhead and improves write performance.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system maintains continuity of useful action by enabling concurrent write operations. While updated data is being written to replace original data in a stripe, unrelated data is simultaneously written to the same stripe. This continuous utilization of write channels eliminates idle time and improves overall productivity without requiring read-copy operations.

Inventive Principle:
Principle #20Continuity of useful action

2Reliability

If error detection and removal operations are performed on stripes, then data integrity is improved, but operational complexity increases

Engineering Contradiction:
Improvedata integrityVSAvoiderror handling complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system implements self-service error handling where the memory subsystem automatically detects errors in stripes and performs removal operations without external intervention. The control circuitry monitors stripe integrity, identifies erroneous stripes, and removes them from the active stripe set automatically. This self-service approach improves data integrity while minimizing the complexity burden on external error handling mechanisms.

Inventive Principle:
Principle #25Self-service

3Productivity

If unrelated data is written concurrently with updated data, then throughput is improved, but error detection difficulty increases

Engineering Contradiction:
Improvewrite throughputVSAvoiderror detection difficulty
Core Design Contradiction:
ProductivityVSDifficulty of detecting and measuring

Solution Approach 1:

The system applies segmentation by organizing concurrent write operations into distinct segments or groups. Updated data and unrelated data are written as separate segments within the same stripe, each with its own error detection and validation mechanisms. This segmentation allows the system to maintain high throughput from concurrent operations while simplifying error detection by isolating errors to specific segments rather than mixing them together.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP2483785B1Stripe-based memory operation
Publication Date: 2017.09.20 MICRON TECHNOLOGY INC
  • EP2483785B1 patent drawingFigure 1
  • EP2483785B1 patent drawingFigure 2
  • EP2483785B1 patent drawingFigure 3

AI summary

The present disclosure includes methods and devices for stripe-based memory operation. One method embodiment includes writing data in a first stripe across a storage volume of a plurality of memory devices. A portion of the first stripe is updated by writing updated data in a portion of a second stripe across the storage volume of the plurality of memory devices. The portion of the first stripe is invalidated. The invalid portion of the first stripe and a remainder of the first stripe are maintained until the first stripe is reclaimed. Other methods and devices are also disclosed.