Stripe-Based Non-Volatile Memory Error Correction via RAID Parity
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently managing and correcting errors in multilevel memory operations, particularly in stripe-based non-volatile memory systems, where uncorrectable errors can lead to data loss and system instability.
Innovation Solution
The implementation of a method that writes information across multiple channels using RAID XOR circuitry to calculate parity information, allowing for error detection and correction by recreating data using parity information stored across different channels, ensuring data integrity and stability in multilevel memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If stripe-based multilevel memory operations are used to increase storage capacity and performance, then productivity and storage efficiency are improved, but the risk of uncorrectable errors and data loss increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing parity information for each stripe before actual data writing operations. The memory controller computes parity data in advance and stores it in dedicated parity pages, so that when data is written to multiple channels, the error correction capability is already in place. This preliminary preparation ensures that even if uncorrectable errors occur during multilevel operations, the pre-stored parity information can immediately be used for data recovery, thus resolving the contradiction between improved storage efficiency and maintained data integrity.
2Reliability
If RAID XOR circuitry is implemented for error correction across multiple channels, then data reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the error correction function into separate, dedicated components for each stripe. Instead of implementing a single complex global XOR circuit, the system creates multiple independent parity calculation units, each handling a specific stripe's parity information. This segmentation allows the system to achieve comprehensive error correction coverage across all channels while keeping each individual circuit module relatively simple and manageable, thus resolving the contradiction between improved reliability and reduced device complexity.
3Loss of information
If parity information is stored across different channels to enable error recovery, then loss of information is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by dedicating specific pages within each channel to store parity information for corresponding stripes. Instead of uniformly distributing all data and parity across channels, the system creates localized parity storage regions with specific functions. Each channel has designated parity pages that store correction data for particular data pages, allowing for targeted error recovery. This localized approach reduces the overall programming precision requirements compared to uniform distribution, as parity information can be independently managed and verified for each local region, thus resolving the contradiction between reduced data loss and lowered manufacturing precision requirements.
Data Source
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AI summary
Stripe-based non-volatile multilevel memory operation can include writing a plurality of lower stripes including programming a plurality of lower pages of information in each of the plurality of lower stripes. A plurality of upper stripes can be written including programming a plurality of upper pages of the information in each upper stripe. Each of the plurality of upper pages in a particular one of the plurality of the upper stripes corresponds to a respective lower page in a different one of the plurality of lower stripes.