Striped Trench and Contact Window Orientation in Semiconductor Devices
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Solution Overview
Problem
Conventional semiconductor devices face challenges in achieving reduced cell sizes, higher cell densities, lower on-resistance, and lower gate charge, particularly in superjunction devices used for high-voltage applications.
Innovation Solution
The semiconductor device features a striped orientation of trenches and contact windows, where trenches are spaced apart parallel to a gate axis, and contact windows are arranged in parallel rows between the trenches, separated only by a dielectric layer, allowing for reduced gate charge and on-resistance through optimized doping and etching techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a grid pattern of trenches and contact windows is used, then the device structure is conventional and easy to manufacture, but the cell size is large and cell density is low
Solution Approach 1:
The patent transitions from a two-dimensional grid pattern to a one-dimensional striped pattern, arranging trenches and contact windows in parallel rows rather than intersecting grids. This dimensional simplification reduces the number of features per cell while maintaining manufacturability, thereby increasing cell density without significantly complicating the fabrication process
2Ease of manufacture
If a grid pattern of trenches and contact windows is used, then the manufacturing process is simple, but the on-resistance is high
Solution Approach 1:
The patent optimizes the local arrangement of contact windows relative to trenches, positioning them in parallel rows to improve current distribution and reduce localized resistance. This localized optimization of the contact-trench configuration lowers overall on-resistance while keeping the manufacturing process relatively simple
3Device complexity
If conventional trench and contact window arrangement is used, then the gate charge is high, but the device structure is simpler
Solution Approach 1:
The patent segments the gate structure into regions associated with individual parallel rows of trenches and contact windows. This segmentation allows for optimized electric field distribution and reduced capacitive coupling, thereby lowering gate charge requirements while maintaining a relatively simple overall device structure
Data Source
AI summary
A semiconductor device includes a semiconductor layer having first and second main surfaces, with the first surface defining a plane containing first and second perpendicular axes. A first gate is disposed proximate the first main surface and extends parallel to the first axis. A dielectric layer is formed on the first main surface and separates the first gate from the first main surface. First and second trenches are formed in the semiconductor layer proximate the first gate and spaced apart in a direction parallel to the first axis. First and second pluralities of contact windows are formed in the dielectric layer to expose the first main surface and are respectively arranged in first and second rows extending between the first and second trenches in a direction parallel to the first axis. Adjacent contact windows in each first row are separated only by the dielectric layer.