Stripped EMIB Layout for Lower-Layer Package Interconnect

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Solution Overview

Problem

Integrated circuit miniaturization faces challenges due to package real estate constraints during interconnecting, where existing technologies struggle to optimize the layer count and signal referencing in integrated-circuit device packages.

Innovation Solution

The implementation of a stripped embedded multi-die interconnect bridge (sEMIB) is seated just below the top solder-resist layer, fabricated on a glass substrate, and then stripped, allowing for a low Z-height and thinner upper dielectric layers, which reduces the package-layer count from 4-2-4 to 3-2-3, enhancing signal referencing and saving valuable interconnect layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional multi-layer package substrate is used, then signal referencing and interconnect capacity are improved, but package real estate consumption and device complexity increase

Engineering Contradiction:
Improvesignal referencingVSAvoidpackage real estate
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts the interconnect bridge function from the traditional multi-layer substrate architecture by implementing a stripped EMIB (embedded multi-die interconnect bridge) structure. This removes the need for extensive substrate layers dedicated to interconnecting, as the bridge is now a separate, optimized component that can be precisely positioned and connected to dies, thereby reducing overall package real estate while maintaining signal integrity.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent transitions from a planar, two-dimensional substrate layout to a three-dimensional stacked architecture using the stripped EMIB. By vertical stacking of dies interconnected through the EMIB bridge, the design achieves higher interconnect capacity and better signal referencing without proportionally increasing the package footprint, effectively utilizing the Z-dimension to reduce real estate consumption.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If package layer count is reduced, then manufacturing complexity and cost are decreased, but signal referencing quality may deteriorate

Engineering Contradiction:
Improvepackage-layer countVSAvoidsignal referencing
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies local quality by concentrating signal referencing resources at critical locations rather than distributing them uniformly across multiple substrate layers. The stripped EMIB provides localized, high-quality signal referencing exactly where needed at the die-EMIB interface, eliminating the need for extensive substrate routing layers while maintaining or improving signal integrity through precision-aligned interconnections.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The stripped EMIB acts as an intermediary component between the substrate and the dies, providing superior signal referencing functionality that eliminates the need for complex multi-layer substrate routing. This mediator structure offers controlled impedance pathways and dedicated reference planes directly at the interconnect interface, achieving better signal quality with fewer overall layers.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Area of stationary object

If stripped EMIB is implemented, then package real estate is optimized and signal referencing is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvepackage real estateVSAvoidalignment precision
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by pre-fabricating the stripped EMIB structure with integrated alignment features and reference marks before die attachment. The EMIB is prepared in advance with precisely positioned vias, traces, and bond pads, allowing for accurate alignment during subsequent die bonding processes. This pre-preparation reduces the precision burden during final assembly by providing built-in registration mechanisms.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11908793B2Stripped redistrubution-layer fabrication for package-top embedded multi-die interconnect bridge
Publication Date: 2024.02.20 INTEL CORP
  • US11908793B2 patent drawing
  • US11908793B2 patent drawing
  • US11908793B2 patent drawing

AI summary

An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.