Data Strobe Clock Buffer Timing Control for Jitter Immunity
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Solution Overview
Problem
Semiconductor memory apparatuses experience data input errors due to sensitive reactions to external data strobe clock signal jitter, caused by inaccurate buffer enable signal timing generated from different clock domains, leading to malfunction and instability in data input operations.
Innovation Solution
A data strobe clock buffer system comprising a buffering block, a timing discriminating block, and an enable controlling block that generates a buffer enable signal based on toggle timing discrimination signals, ensuring unified clock domains and stable data input operations by accurately defining the enable time intervals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If buffer enable signals are generated using external clock signals to define operation intervals of data strobe clock buffers, then the buffers can be controlled to perform buffering operations, but the enable time intervals become inaccurate due to different clock domains and environmental noise, causing data input errors
Solution Approach 1:
The patent introduces an intermediary timing control mechanism that mediates between the external clock domain and the buffer operation control. Instead of directly using external clock signals to generate buffer enable signals, the invention uses internal timing signals derived from the data strobe clock buffer's own output to control the enable intervals, thereby eliminating the clock domain mismatch and improving timing accuracy
Solution Approach 2:
The patent implements a feedback mechanism where the timing control unit monitors the actual operation of the data strobe clock buffer and adjusts the buffer enable signal timing accordingly. The enable signals are generated based on the actual toggle timing of the buffered data strobe clock signals, creating a closed-loop control system that compensates for environmental noise and jitter
2Productivity
If the operational speed of the semiconductor memory apparatus is increased to improve productivity, then data input throughput increases, but sensitivity to small jitter components of external data strobe clock signals and external clock signals increases, causing buffer malfunction and data input errors
Solution Approach 1:
The patent implements dynamic timing adjustment where the buffer enable signal intervals are not fixed but are dynamically adjusted based on the actual toggle timing of the data strobe clock signals. This dynamic control allows the system to adapt to speed variations and jitter components, maintaining reliable operation even at high data input throughput speeds
Solution Approach 2:
The timing control unit generates buffer enable signals in advance based on predicted toggle timing of the data strobe clock signals. By preparing the enable signals beforehand with appropriate timing margins, the system ensures that the buffers are properly enabled before the actual data strobe signals arrive, preventing malfunction at high speeds
3Device complexity
If buffer enable signals are generated without considering different clock domains of external data strobe clock signals and external clock signals, then the system structure remains simple, but the enable time intervals are inaccurate due to adverse influences, leading to unstable data input operations
Solution Approach 1:
The patent introduces a timing control unit as an intermediary layer between the external clock signals and the buffer enable signal generation. This intermediary unit translates the timing requirements into accurate enable signals by referencing the actual data strobe clock buffer output, thereby achieving stable data input operations without significantly increasing system complexity
Solution Approach 2:
The patent creates equipotential timing conditions by ensuring that the buffer enable signals are synchronized with the same clock domain as the data strobe clock signals. The timing control unit generates enable signals that are equipotential with respect to the data strobe clock timing, eliminating timing mismatches and improving operational stability
Data Source
AI summary
A data strobe clock buffer of a semiconductor memory apparatus includes a buffering block configured to buffer an external data strobe clock signal in response to a buffer enable signal to generate an internal data strobe clock signal, a timing discriminating block configured to discriminate toggle timing of the internal data strobe clock signal in response to a burst start signal and a burst length signal to generate a timing discrimination signal, and an enable controlling block configured to generate the buffer enable signal in response to the timing discrimination signal.