Buffer Chip Strobe Training for High-Speed Memory Signal Skew
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing storage devices face challenges in aligning communication signals at high operating frequencies, leading to potential communication errors and reduced performance due to signal skew and duty mismatch between memory chips and the controller.
Innovation Solution
A storage device with a buffer chip that includes a delay circuit, sampler, comparator, and counter module to perform per-pin training by transmitting random data and strobe signals, determining a target delay, and adjusting the strobe signal to align phases and correct duty cycles, thereby improving communication accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high operating frequency communication is implemented in storage devices, then communication speed is improved, but signal alignment accuracy deteriorates due to signal skew and duty mismatch
Solution Approach 1:
The patent performs delay training and duty cycle training in advance before normal high-speed communication begins. The buffer chip determines optimal delay values and duty cycle values through training sequences, then applies these settings beforehand to ensure accurate signal alignment when actual data transmission starts at high frequency.
Solution Approach 2:
The patent employs feedback mechanisms where the buffer chip monitors communication quality and adjusts delay and duty cycle values based on detected signal characteristics. The training process involves comparing transmitted and received signals to determine optimal alignment parameters, creating a closed-loop system that ensures signal integrity at high operating frequencies.
2Measurement precision
If separate phase alignment and duty cycle correction are performed, then signal alignment accuracy is improved, but training time increases
Solution Approach 1:
The patent combines phase alignment (delay training) and duty cycle correction into a single integrated training process. The buffer chip simultaneously determines both the optimal delay value and duty cycle value during one training sequence exchange, eliminating the need for separate training phases and reducing overall training time while maintaining signal alignment accuracy.
3Device complexity
If delay training is performed using traditional methods without buffer chip, then device complexity is reduced, but communication reliability deteriorates at high frequencies
Solution Approach 1:
The patent introduces a buffer chip as an intermediary component between the memory device and controller. This buffer chip performs delay training and duty cycle correction, acting as a mediator that ensures reliable high-frequency communication. The buffer chip absorbs the complexity of signal alignment tasks, allowing the memory device and controller to maintain simpler designs while achieving improved communication reliability.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A storage device includes a buffer chip and a memory device. The memory device transmits a random data signal and a data strobe signal to the buffer chip based on a clock signal received from the buffer chip. The buffer chip includes a delay circuit that delays the data strobe signal by a delay time to generate a delayed data strobe signal, a sampler that receives the delayed data strobe signal from the delay circuit and samples the random data signal based on the delayed data strobe signal to generate sampled data, a comparator that compares internal data with the sampled data to generate a comparison result, and a counter module that receives the comparison result from the comparator and determines a target delay based on the comparison result. The buffer chip delays the delayed data strobe signal based on the target delay.