Strobe Technique for Digital Signal Time Stamping
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Solution Overview
Problem
Automatic test equipment (ATE) faces challenges in accurately measuring digital signal timing due to signal slewing and jitter, especially when testing high-speed signals, and accessing a device's internal synchronous clock is impractical without tying up valuable test system hardware channels.
Innovation Solution
Generating a time-stamp by routing an external clock signal through a series of delays and applying strobe pulses to parallel latches to capture samples of the digital signal, with an encoder converting these samples into a word representing edge time and polarity, and using a counter to determine the precise time of the clock edge for comparison.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a test system clock is used to measure data signals on a synchronous bus, then timing measurements can be obtained, but measurement precision deteriorates due to high jitter relative to the test system clock
Solution Approach 1:
The patent introduces an intermediary clock signal that is phase-locked to the DUT's synchronous clock. This intermediary clock serves as a mediator between the test system clock and the data signals, allowing timing measurements to be taken without direct comparison to the high-jitter synchronous clock. The intermediary clock absorbs the jitter through phase-locking while providing a stable reference for measurement.
Solution Approach 2:
The patent changes the parameter of the clock signal by generating multiple copies of the synchronous clock with different phase offsets. By varying the phase parameter and selecting the optimal phase alignment, the system achieves accurate timing measurements despite the inherent jitter in the original synchronous clock signal.
2Measurement precision
If the DUT's synchronous internal clock is accessed for timing measurements, then accurate relative timing can be obtained, but device complexity increases due to hardware channel requirements
Solution Approach 1:
The patent creates multiple copies of the synchronous clock signal through phase shifting and delay circuits. These copied clock signals are used to sample the data bus at different phase points, eliminating the need to directly access the internal DUT clock while maintaining measurement accuracy. The copying approach reduces hardware complexity by using external signal generation rather than internal clock access.
Solution Approach 2:
The patent segments the clock signal into multiple phase-shifted copies, each used for sampling different portions of the data bus. This segmentation allows the system to measure timing across the entire bus width without requiring a single complex hardware channel, distributing the measurement function across multiple simpler parallel channels.
3Speed
If high-speed data signals are tested relative to the DUT's system clock, then functional testing can be performed, but measurement precision deteriorates due to signal slewing and jitter
Solution Approach 1:
The patent employs periodic sampling using phase-shifted clock copies to capture data signals at multiple points within the clock cycle. By taking periodic measurements at different phase offsets and combining the results, the system achieves accurate timing measurement of high-speed signals while accounting for slewing and jitter effects that occur during the clock period.
Data Source
AI summary
A system and apparatus generates a time-stamp to identify and record the time of an event such as an edge received in a data signal or clock signal. A set of strobe pulses can be generated by routing an external clock signal to delay elements with incrementally increasing delay values. A data signal or device under test clock signal can be applied to the input to each of a set of latches which are clocked by the strobe pulses. The set of latches can thereby capture a series of samples of the data signal or clock signal. The series of samples can be encoded as an edge time within a clock cycle. A clock cycle counter can be added to the edge time to generate the time stamp.