Strobe-less Data Buffer for Memory Capacity and Integrity
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Solution Overview
Problem
Current memory interfaces for central processing units (CPUs) face limitations on memory capacity and bandwidth, leading to diminished data transfer integrity as the number of memory devices increases, which hampers data processing speed.
Innovation Solution
The implementation of a memory-buffer architecture with distributed data buffers on each DIMM, which buffers data signals and uses forwarded clocking to create a strobe-less secondary interface between DRAM devices and data buffers, optimizing power consumption and performance by eliminating the need for strobe signals and enabling clock gating for inactive ranks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory devices is increased to enhance memory capacity and bandwidth, then data transfer capacity improves, but data transfer integrity deteriorates due to bus loading
Solution Approach 1:
The patent introduces a data buffer as an intermediary component between the memory controller and DRAM devices. The buffer receives data signals from the memory controller and forwards them to multiple DRAM devices without requiring all devices to share the same bus, thereby maintaining data transfer integrity while enabling increased memory capacity through distributed buffering architecture
Solution Approach 2:
The patent segments the data transfer path by distributing data buffers across multiple DIMMs rather than using a centralized buffer. Each DIMM has its own local buffer that independently manages data transfer to its associated DRAM devices, eliminating bus contention and maintaining integrity even as the total number of memory devices increases
2Ease of operation
If strobe signals are used to control data transfer timing, then data transfer control is achieved, but power consumption increases
Solution Approach 1:
The patent changes the timing control parameter from strobe-based edge-triggered control to clock-based level-triggered control. By using forwarded clock signals that are already present in the DRAM devices, the system eliminates the need for additional strobe signals, thereby reducing power consumption while maintaining precise data transfer timing control
Solution Approach 2:
The DRAM devices utilize their own internal clock signals to control data transfer timing instead of requiring external strobe signals. The data buffer forwards the clock signal directly to the DRAM devices, allowing the DRAM devices to self-regulate their timing based on their internal clock, thereby eliminating redundant signaling and reducing power consumption
3Productivity
If distributed data buffers are implemented on each DIMM, then memory capacity and bandwidth are enhanced, but device complexity increases
Solution Approach 1:
The patent divides the buffering function across multiple independent DIMM modules, with each DIMM containing its own local data buffer. This segmentation allows each buffer to operate independently, simplifying the design of individual buffer units while collectively providing high memory capacity and bandwidth through parallel operation of multiple DIMMs
Solution Approach 2:
The data buffer is designed as a universal component that can be implemented on any DIMM and performs multiple functions: data buffering, signal amplification, timing control, and isolation. This multi-functionality reduces the need for additional specialized components, thereby managing overall system complexity while enhancing productivity
Data Source
AI summary
A data buffer with a strobe-based primary interface and a strobe-less secondary interface used on a memory module is described. One memory module includes an address buffer, the data buffer and multiple dynamic random-access memory (DRAM) devices. The address buffer provides a timing reference to the data buffer and to the DRAM devices for one or more transactions between the data buffer and the DRAM devices via the strobe-less secondary interface.