Internal Strobe Phase Matching for High-Speed Semiconductor I/O

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

High-speed semiconductor systems face challenges in maintaining phase synchronization between strobe signals and commands due to delay discrepancies in data transfer paths, leading to potential errors in data input/output operations.

Innovation Solution

A system utilizing a Delay-Locked Loop (DLL) clock to compensate for delay amounts in both the command and strobe signal paths, generating internal strobe signals to synchronize phases and ensure accurate data transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If clock dividing technique is used to increase data transfer rate, then productivity is improved, but phase synchronization between strobe signal and command deteriorates due to path delay discrepancies

Engineering Contradiction:
Improvedata transfer rateVSAvoidphase synchronization
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by compensating for path delays before the data transfer operation occurs. The system calculates the delay difference between the command path and strobe signal path in advance, then adjusts the strobe signal phase accordingly before deserialization begins, ensuring phase synchronization is established proactively rather than reactively

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms to monitor and maintain phase synchronization between the strobe signal and command. The system continuously tracks the phase relationship and adjusts the strobe signal timing based on detected synchronization status, creating a closed-loop control system that maintains reliability during high-speed operations

Inventive Principle:
Principle #23Feedback

2Productivity

If multi-phase clocks are generated for high-speed data input/output, then productivity is improved, but device complexity increases due to additional phase matching requirements

Engineering Contradiction:
Improvedata transfer rateVSAvoidphase matching circuitry
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts the delay compensation function from the main data transfer path and implements it as a separate preprocessing stage. By isolating the delay calculation and compensation mechanisms into dedicated circuits that operate independently from the core deserialization logic, the system manages complexity while maintaining high-speed performance

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the signal processing into distinct functional blocks: command path processing, strobe signal path processing, delay calculation unit, and phase adjustment unit. This segmentation allows each component to be optimized independently and simplifies the overall system architecture by clearly defining interfaces between modules

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20210327478A1System for performing phase matching operation
Publication Date: 2021.10.21 SK HYNIX INC
  • US20210327478A1 patent drawing
  • US20210327478A1 patent drawing
  • US20210327478A1 patent drawing

AI summary

A system for performing a phase matching operation includes a controller configured to output a clock, a command, and a strobe signal, and to input/output data. The system also includes a semiconductor device configured to generate an internal strobe signal by matching the phases of the command and the strobe signal according to the clock, and to input/output the data in synchronization with the internal strobe signal, wherein the semiconductor device generates the internal strobe signal from the strobe signal by compensating for a delay amount of a first path to which the command is inputted and a delay amount of a second path to which the strobe signal is inputted.