Strobe Signal Synchronization for Semiconductor Memory
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Solution Overview
Problem
Existing semiconductor systems face challenges in synchronizing data input/output operations efficiently, leading to increased power consumption and decreased operation speed due to the need for high-power phase-locked loop (PLL) circuits, especially in low-power devices like mobile devices, and hindered bandwidth and operation speed due to PLL activation and deactivation times.
Innovation Solution
A semiconductor system that generates a second strobe signal by delaying a first strobe signal, allowing data to be synchronized with the center of the strobe signal without requiring a PLL or DLL circuit, thereby improving data output margin and bandwidth without increasing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a phase-locked loop (PLL) circuit is used to synchronize data input/output operations, then data synchronization precision is improved, but power consumption increases
Solution Approach 1:
The patent extracts and eliminates the PLL circuit from the memory system, replacing it with a simpler strobe signal-based synchronization mechanism. The controller generates strobe signals that directly synchronize data transfer without requiring the complex phase-locked loop circuitry, thereby removing the power-consuming component while maintaining synchronization capability.
Solution Approach 2:
The patent changes the synchronization parameter from phase-locked loop control to strobe signal timing control. By using strobe signals with specific timing relationships to data transfer operations, the system achieves synchronization through parameter-based timing control rather than through the power-intensive PLL mechanism.
2Speed
If a phase-locked loop (PLL) circuit is activated for high-speed data transfer, then operation speed is improved, but bandwidth is reduced due to activation and deactivation times
Solution Approach 1:
The patent implements preliminary action by pre-generating and providing strobe signals to the memory apparatus before data transfer operations begin. The controller has continuous access to strobe signals, eliminating the need for PLL activation delays. Data transfer can start immediately when data is ready, as synchronization signals are already available, thus removing activation/deactivation overhead and increasing effective bandwidth.
3Reliability
If a phase-locked loop (PLL) circuit is used for data synchronization, then data output margin is improved, but device complexity increases
Solution Approach 1:
The patent uses strobe signals as a simplified copy or alternative to the PLL synchronization mechanism. Instead of implementing the complex PLL circuitry, the system copies the essential synchronization function using simpler timed strobe signals that replicate the phase-locking behavior without the associated complexity and power consumption.
Data Source
AI summary
A semiconductor system, a semiconductor memory apparatus, and a method for input/output of data using the same are disclosed. The semiconductor system includes a controller and a memory apparatus where the controller is configured to transmit a clock signal, a data output command, an address signal, and a second strobe signal to a memory apparatus. The memory apparatus is configured to provide data to the controller in synchronization with the second strobe signal, and in response to the clock signal, the data output command, the address signal, and the second strobe signal received from the controller.