Strobe Technique for Digital Signal Timing Test

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Solution Overview

Problem

Automatic test equipment faces challenges in accurately measuring the timing of semi-conductor chips due to signal slewing and jitter, especially when testing synchronous buses, as it is impractical to access the internal clock without tying up valuable hardware channels and using a test system clock introduces high jitter issues.

Innovation Solution

The method involves generating closely spaced strobe pulses to sample data and clock signals, encoding edge times and polarities, and comparing these to emulate the synchronous clock of the device under test, allowing for accurate timing evaluation without direct access to the internal clock.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a test system clock is used to test data on synchronous buses, then testing can be performed without accessing the internal clock, but measurement accuracy deteriorates due to high jitter relative to the test system clock

Engineering Contradiction:
Improveability to test synchronous busVSAvoidtiming measurement accuracy
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The patent creates a copy of the DUT's internal clock signal through the synchronous clock input and uses this copied clock to generate strobe pulses for sampling. This allows the test system to emulate the internal clock's timing characteristics without directly accessing it, thereby maintaining measurement accuracy while preserving ease of operation.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent introduces a synchronous clock input and associated circuitry as an intermediary between the test system clock and the sampling mechanism. This intermediary allows the system to translate the test clock into strobe pulses that are synchronized with the DUT's internal clock timing, resolving the jitter problem while maintaining testability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If closely spaced strobe pulses are generated to sample data signals, then timing measurement accuracy is improved, but device complexity increases due to additional delay elements and strobe generation circuitry

Engineering Contradiction:
Improvetiming measurement accuracyVSAvoidstrobe generation circuitry
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the strobe generation function into multiple parallel delay elements, each creating a slightly delayed version of the clock signal. This segmentation allows the system to generate multiple strobe pulses with precise timing relationships, improving measurement accuracy while distributing the complexity across simple, identical components.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses periodic clock signals as the basis for generating the strobe pulses. By deriving the strobe sequence from a periodic clock source through systematic delay, the system achieves accurate timing measurements while leveraging the simplicity and predictability of periodic waveforms rather than requiring complex arbitrary waveform generation.

Inventive Principle:
Principle #19Periodic action

3Measurement precision

If the internal clock is accessed directly for timing measurements, then measurement accuracy is improved, but hardware channels are tied up and productivity decreases

Engineering Contradiction:
Improvetiming measurement accuracyVSAvoidtest system throughput
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent creates a functional copy of the internal clock signal through the synchronous clock input, allowing timing measurements to be performed on this copy rather than requiring direct access to the internal clock. This preserves measurement accuracy while freeing the internal clock to continue its primary function, thereby maintaining productivity.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The synchronous clock input serves as an intermediary that provides the timing reference needed for accurate measurements without requiring direct access to the internal clock. This intermediary mechanism allows the internal clock to remain unavailable for other purposes while still enabling precise timing measurements through the proxy clock signal.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS7856578B2Strobe technique for test of digital signal timing
Publication Date: 2010.12.21 TERADYNE INC
  • US7856578B2 patent drawing
  • US7856578B2 patent drawing
  • US7856578B2 patent drawing

AI summary

A test system timing method simulates the timing of a synchronous clock on the device under test. Strobe pulses can be generated by routing an edge generator to delay elements with incrementally increasing delay values. A data signal or synchronous clock signal can be applied to the input of each of a set of latches which are clocked by the strobe pulses. An encoder can convert the series of samples which are thereby latched to a word representing edge time and polarity of the sampled signal. If the sampled signal is a data signal, the word can be stored in memory. If the sampled signal is a clock signal, the word is routed to a clock bus and used to address the memory. The difference between clock edge time and data edge time is provided and can be compared against expected values.