Strobe Enable Window Generation for Frequency-Agile Memory Reads
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Solution Overview
Problem
Clocked memory systems face challenges in synchronizing data and timing reference signals due to varying delays caused by temperature and supply voltage changes, especially when the clock frequency changes, leading to uncertainty in the phase relationship between the memory controller's clock domain and the returned timing reference signal.
Innovation Solution
A synchronization circuit with two cascaded calibration loops is used to track both cycle-dependent and cycle-independent delays in the read path, generating a timing-enable signal that adapts to frequency changes by separating delays into components that are dependent or independent of the clock frequency, allowing for precise synchronization of the strobe signal with the read data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the signaling rate is increased to improve data transmission speed, then productivity is improved, but the phase relationship uncertainty between clock domain and timing reference signal worsens due to varying delays
Solution Approach 1:
The patent implements dynamic delay adjustment by making the delay applied to the timing reference signal variable rather than fixed. The delay is adjusted based on detected phase relationships between the clock domain and timing reference signal, allowing the system to adapt to changing operating conditions while maintaining synchronization accuracy at high signaling rates
Solution Approach 2:
The patent employs feedback mechanisms where the phase relationship between the clock domain and timing reference signal is continuously detected and used to adjust the delay. This closed-loop control ensures that despite variations in temperature, voltage, or signaling rate, the timing reference signal remains properly synchronized with the clock domain
2Measurement precision
If the communication path length is reduced to improve synchronization, then measurement precision is improved, but device complexity increases due to the need for delay adjustment circuitry
Solution Approach 1:
The patent segments the delay adjustment into discrete selectable delay values that can be implemented using standard digital logic components. By dividing the delay adjustment into manageable segments rather than requiring continuous analog adjustment, the implementation complexity is reduced while maintaining synchronization precision
Solution Approach 2:
The patent introduces an intermediary delay element between the timing reference signal path and the data path. This intermediary component acts as a buffer that can be dynamically adjusted to compensate for path length variations, allowing the use of longer communication paths without sacrificing synchronization accuracy
3Reliability
If temperature and supply voltage are stabilized to reduce delay variations, then reliability is improved, but use of energy increases due to additional stabilization circuitry
Solution Approach 1:
The patent implements self-service by using the existing timing reference signal and clock domain signals to detect phase relationships and control the delay adjustment. Rather than requiring separate stabilization circuits that consume additional power, the system uses its own operational signals to automatically compensate for temperature and voltage variations
Data Source
AI summary
The disclosed embodiments relate to components of a memory system that support frequency-agile strobe enable window generation during read accesses. In specific embodiments, this memory system contains a memory controller which includes a timing circuit to synchronize a timing-enable signal with a timing signal returned from a read path, wherein the timing signal includes a delay from the read path. In some embodiments, the timing circuit further comprises two calibration loops. The first calibration loop tracks the timing-enable signal with respect to a cycle-dependent delay in the delay, wherein the cycle-dependent delay depends on a frequency of the strobe signal. The second calibration loop tracks the timing-enable signal with respect to a cycle-independent delay in the delay, wherein the cycle-independent delay does not depend on the frequency of the strobe signal. In some embodiments, the first calibration loop and the second calibration loop are cascaded.