Strobeless DRAM Data Interface With Drift Tracking Timing Alignment
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Solution Overview
Problem
Existing memory systems face challenges in managing phase skew and phase drift due to varying path lengths in fly-by and point-to-point signaling paths, leading to timing errors and increased pin count and power consumption.
Innovation Solution
The implementation of a drift tracking circuitry within memory controllers and devices that adjusts data reception timing using phase information from data burst toggling edges, reducing the need for external strobe signals and minimizing pin count and power consumption by generating internal strobe signals, and employing calibration and oversampling techniques to correct for phase drift.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external strobe signals are used for data reception timing, then timing accuracy is improved, but pin count and power consumption increase
Solution Approach 1:
The patent extracts the strobe signal generation function from external sources and implements it internally within the memory device. The drift tracking circuitry generates internal strobe signals based on phase information from data bursts, eliminating the need for external strobe signal pins while maintaining timing accuracy.
Solution Approach 2:
The data burst signals serve multiple functions: they carry actual data information and simultaneously provide phase information for timing synchronization. The toggling edges of data bursts are utilized to update drift tracking, making the data signals multi-functional and eliminating the need for separate strobe signals.
2Measurement precision
If external strobe signals are used for data reception timing, then timing accuracy is improved, but power consumption increases
Solution Approach 1:
The patent extracts the strobe signal generation function from external sources and implements it internally within the memory device. The drift tracking circuitry generates internal strobe signals based on phase information from data bursts, eliminating the need for external strobe signal pins while maintaining timing accuracy.
Solution Approach 2:
The memory device performs self-synchronization by using its own data burst toggling edges to update drift tracking and generate internal strobe signals. This self-service approach eliminates the need for external timing signals and reduces power consumption associated with external signal transmission and reception.
3Measurement precision
If drift tracking circuitry is implemented, then timing accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges the drift tracking functionality with the existing data reception circuitry. The same circuitry that receives data bursts also extracts phase information from toggling edges for drift tracking updates, combining multiple functions into unified circuit blocks and reducing overall device complexity.
Solution Approach 2:
The data burst signals serve multiple functions: they carry actual data information and simultaneously provide phase information for timing synchronization. The toggling edges of data bursts are utilized to update drift tracking, making the data signals multi-functional and eliminating the need for separate strobe signals.
4Measurement precision
If calibration techniques are employed, then timing drift is corrected, but manufacturing complexity increases
Solution Approach 1:
The patent implements preliminary calibration during the manufacturing process to establish initial timing parameters. Drift tracking circuitry is pre-configured with calibration data that compensates for process variations, allowing the system to achieve accurate timing without complex post-manufacturing adjustments or additional manufacturing steps.
Data Source
AI summary
Memory devices, modules, controllers, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory chip is disclosed. The IC memory chip includes clock receive circuitry to receive a clock signal and command/address (C/A) receive circuitry to time reception of C/A signals using the clock signal. Data receive circuitry receives a first data burst from a first data path. Calibration circuitry sets an initial sampling phase for data reception timing of the first data burst relative to the clock signal. Timing circuitry tracks drift in the data reception timing using phase information from at least one toggling edge of the data burst and adjusts the data reception timing based on the phase information.