Strong PUF With Dual-Edge Sampling For ML Attack Resistance
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Solution Overview
Problem
Existing strong PUFs struggle to achieve machine learning attack resistance while maintaining small hardware expenditure and generating a large number of challenge response pairs.
Innovation Solution
A machine learning attack resistant strong PUF with a dual-edge sampling function is designed, comprising N switch units and two arbiters. Each switch unit has a unique configuration of PMOS and NMOS transistors that allow for parallel or crossed transmission of square signals under challenge signal control, enabling dual-edge sampling and increased challenge response pairs generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional PUF structures are used to generate challenge response pairs, then the hardware area is small, but the resistance to machine learning attacks is weak
Solution Approach 1:
The PUF structure is divided into multiple switch units (N switch units) connected in series, where each switch unit contains multiple transistors arranged in specific paths. This segmentation allows the system to achieve higher security through increased complexity without requiring a single large monolithic structure, thereby improving machine learning attack resistance while controlling hardware area.
Solution Approach 2:
The patent introduces a dual-edge sampling mechanism that processes both rising edges and falling edges of clock signals. This adds a temporal dimension to the challenge response pair generation, effectively doubling the information content per clock cycle without proportionally increasing hardware area, thus improving security metrics while maintaining area efficiency.
2Reliability
If more challenge response pairs are generated to improve security, then the machine learning attack resistance increases, but the hardware expenditure increases
Solution Approach 1:
Each switch unit is designed to handle multiple functions: it processes both rising and falling edges of clock signals, supports parallel signal transmission paths, and generates multiple challenge response pairs through different transistor combinations. This multi-functionality allows the same hardware structure to generate a large number of CRPs without proportionally increasing hardware expenditure.
Solution Approach 2:
The patent utilizes periodic clock signals with dual-edge sampling, where both the rising edge and falling edge of each clock cycle are used for sampling. This periodic action effectively doubles the CRP generation rate without requiring double the hardware, as the same physical structures are reused at different time points within each clock period.
3Productivity
If dual-edge sampling is implemented to increase CRP generation, then the number of challenge response pairs increases, but the circuit complexity increases
Solution Approach 1:
The patent merges the processing of rising edges and falling edges into a unified circuit structure where the same switch units and transistor networks handle both edge types. By combining these functions into shared hardware resources rather than duplicating separate circuits, the system achieves high CRP generation rates while controlling circuit complexity through resource sharing and functional integration.
Data Source
AI summary
A machine learning attack resistant strong PUF with a dual-edge sampling function comprises switch units, a first arbiter and a second arbiter. The first arbiter is for determining a sequential order of delays at a rising edge of signals input to a first input terminal and a second input terminal of the first arbiter. The second arbiter is for determining a sequential order of delays at a falling edge of signals input to a first input terminal and a second input terminal of the second arbiter. Each switch unit is composed of eight MOS transistors. The strong PUF has a high capacity to resist machine learning attacks and small hardware expenditure through simple structural design of the switch units, realizing machine learning attack resistance and small hardware expenditure at the same time, and generating a large number of challenge response pairs through dual-edge sampling realized by the two arbiters.