StrongArm Comparator Reset Timing for Asynchronous SAR ADC LSB Accuracy
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Solution Overview
Problem
Existing asynchronous SAR ADCs face challenges in achieving high conversion speed, minimizing power consumption, and reducing chip area while maintaining performance metrics, particularly due to variable internal clock cycles and potential Tbudget violations that can result in lost LSB bits.
Innovation Solution
The introduction of a StrongArm comparator with a modified reset mechanism, incorporating a shunt unit controlled by a second clock signal with a delayed leading edge, separates the reset phases of the comparator and CDAC, allowing for independent control and ensuring completion of LSB conversions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single reset signal is used for both comparator and CDAC in existing asynchronous SAR ADCs, then the control logic is simplified, but Tbudget violations occur resulting in lost LSB bits and reduced conversion accuracy
Solution Approach 1:
The reset function is segmented into two independent reset signals: a first reset signal for the comparator and a second reset signal for the CDAC. This segmentation allows independent control of reset timing for each module, preventing Tbudget violations that cause LSB bit loss while maintaining conversion accuracy.
2Speed
If the reset timing is not optimized in existing asynchronous SAR ADCs, then the circuit operation is simplified, but conversion speed is limited and power consumption increases
Solution Approach 1:
The reset signals are designed to be generated in advance of the clock signals they control. The first reset signal is generated before the first clock signal to prepare the comparator, and the second reset signal is generated before the second clock signal to prepare the CDAC. This preliminary action ensures modules are ready for operation, improving conversion speed while allowing optimized power management.
Solution Approach 2:
The reset mechanism uses dynamic timing control where the duration and timing of reset signals are optimized based on operational requirements. The first reset signal has a duration optimized for comparator reset, while the second reset signal has a duration optimized for CDAC reset, allowing each module to operate efficiently at optimal speeds with minimized power consumption.
3Adaptability or versatility
If variable internal clock cycles are used in existing asynchronous SAR ADCs, then the ADC adapts to different conversion requirements, but Tbudget violations occur causing lost LSB bits
Solution Approach 1:
The system uses feedback control where the variable internal clock cycles are monitored and the reset signal timing is adjusted accordingly. When clock cycle variations approach Tbudget limits, the reset timing is dynamically adjusted to prevent violations, ensuring LSB bit accuracy is maintained while preserving the adaptability benefits of variable clocking.
Data Source
AI summary
Provided are a StrongArm comparator and an SAR ADC. The StrongArm comparator includes an input module, a latch module, a first reset unit and a shunt unit. The input module is configured to receive a pair of differential input voltages, and the latch module is configured to generate a pair of differential output voltages. Operation of the first reset unit is controlled by a first clock signal, discharging of the coupling nodes of the input and latch modules through the input module is activated by an active pulse of the first clock signal, and discharging of the coupling nodes through the shunt unit is activated by an active pulse of a second clock signal, where a leading edge of the active pulse of the second clock signal lags behind the active pulse of the first clock signal, and trailing edges of the first and second clock signals end simultaneously.