Structured ASIC Delay Calculation Using Clock Circuit Library
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Solution Overview
Problem
Conventional delay calculation methods for structured ASICs wastefully repeat delay calculations for clock circuits, increasing design time and resources when designing multiple integrated circuits with the same clock circuit layout patterns.
Innovation Solution
A clock circuit delay library is created to store delay calculation results for a commonly integrated clock circuit, allowing for efficient reuse of this data across various structured ASICs, reducing the need for repetitive calculations and shortening the design time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If delay calculations are performed separately for each structured ASIC design, then accurate delay estimation is achieved, but design time and computational resources are wastefully increased
Solution Approach 1:
The patent applies preliminary action by pre-calculating delay values for clock circuits and storing them in a delay library before actual ASIC design. When designing structured ASICs, the system directly retrieves pre-computed delay data from the library rather than performing repeated calculations, thus maintaining accurate delay estimation while dramatically reducing design time and computational resource consumption.
2Reliability
If conventional delay calculation methods are used for multiple structured ASICs with the same clock circuit layout, then individual accuracy is maintained, but computational resources are wastefully consumed
Solution Approach 1:
The patent applies copying by creating a delay library that stores delay calculation results from a reference clock circuit design. This library can be copied and applied to multiple structured ASIC designs that use the same or similar clock circuit layouts, ensuring consistent and reliable delay calculations while eliminating redundant computational work and significantly improving design efficiency.
3Measurement precision
If delay calculations are repeated for every structured ASIC design, then up-to-date delay data is obtained, but resource consumption and TAT increase
Solution Approach 1:
The patent pre-computes and stores delay data in a library during the preliminary design phase. This preliminary action ensures that accurate and up-to-date delay data is available for subsequent ASIC designs without requiring repeated computational calculations, thus maintaining data currency while minimizing energy consumption and resource usage during actual design operations.
Data Source
AI summary
A delay calculation apparatus is provided for delay calculation of a structured ASIC in which a clock circuit is integrated within a master slice. The delay calculation apparatus is composed of a storage unit storing a clock circuit delay library containing clock circuit delay data obtained by delay calculation of a clock circuit, and a delay calculation section performing delay calculation of a structured ASIC incorporating the clock circuit to thereby generate delay calculation result data of the structured ASIC. The delay calculation section is designed to obtain at least a portion of the clock circuit delay data from the clock circuit delay library, and to merge the obtained portion of the clock circuit delay data into the delay calculation result data.