Structured ASIC Wiring Zones and L-Shaped Driver Cells
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Solution Overview
Problem
Existing semiconductor circuits face challenges in cost-effective production and efficient configuration of driver resources, leading to issues with signal propagation delays and unnecessary driver resource utilization.
Innovation Solution
A structured ASIC with a regular array of logic function blocks and wiring zones, where wiring layers are designed with continuous line segments interrupted at zone boundaries, allowing for customizable signal routing with fewer vias and enabling deeper layer customization, along with a driver cell surrounding logic cells for optimized driver resource allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If mask-programmable wiring layers are used for signal routing customization, then adaptability of signal routing is improved, but manufacturing complexity and cost increase due to high individuality of metallization masks
Solution Approach 1:
The wiring structure is divided into fixed wiring layers (providing regular routing) and mask-programmable wiring layers (providing customizable routing). This segmentation allows the circuit to benefit from both the simplicity of fixed wiring and the flexibility of programmable wiring, reducing overall mask complexity while maintaining adaptability.
Solution Approach 2:
The patent introduces a vertical dimension by stacking multiple wiring layers with different programmability characteristics. Lower layers are fixed while upper layers are mask-programmable, creating a three-dimensional wiring architecture that increases routing capacity without proportionally increasing mask complexity in any single layer.
2Adaptability or versatility
If all wiring planes are created anew for each application, then signal routing adaptability is improved, but manufacturing cost increases due to inability to distribute mask costs
Solution Approach 1:
The fixed wiring layers are predetermined and manufactured in advance using common masks that can be distributed across multiple applications. This preliminary creation of infrastructure wiring reduces per-application mask costs while the mask-programmable layers provide the necessary customization for each specific application.
Solution Approach 2:
The fixed wiring layers serve universal purposes by providing common routing infrastructure that can be used across different applications. This universal wiring backbone allows mask costs to be amortized over multiple products while application-specific customization is achieved through additional programmable layers.
3Speed
If driver resources are distributed to all logic function blocks, then signal propagation delay is reduced, but device complexity increases due to unnecessary driver resource utilization
Solution Approach 1:
Driver resources are selectively placed only in logic function blocks that require them, rather than uniformly distributing drivers across all blocks. This local optimization ensures that signal propagation delays are minimized only where necessary, while avoiding the complexity and overhead of unnecessary driver resources in other blocks.
4Manufacturing precision
If regular array structure is used for logic function blocks, then manufacturing precision is improved, but adaptability decreases due to fixed architecture
Solution Approach 1:
The patent combines a static regular array structure with dynamic configurability through mask-programmable wiring layers and configurable logic elements. The regular physical layout provides manufacturing precision and ease of fabrication, while the programmable aspects allow the logic function and routing to be dynamically adapted to different applications after manufacturing.
Data Source
AI summary
An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.