Structured Glass Substrates for Electronic Packaging
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Solution Overview
Problem
Conventional electronic component packaging results in increased form factor, signal loss, and thermal stress due to mismatched thermal expansion coefficients between polymer substrates and components, leading to processing delays and potential failure.
Innovation Solution
The use of a glass substrate with upper and lower glass cladding layers having a higher etch rate than the glass core layer, allowing for the formation of precise cavities to house microprocessors and other components, minimizing distance and thermal stress while reducing signal loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polymer substrates and polymer adhesives are used to package electronic components, then ease of manufacture is improved, but thermal stress increases due to mismatched thermal expansion coefficients
Solution Approach 1:
The patent changes the material parameter (thermal expansion coefficient) by replacing polymer substrates and adhesives with glass substrates and glass frit adhesives. Glass materials have thermal expansion coefficients that better match electronic components, thereby reducing thermal stress while maintaining manufacturability through established glass processing techniques.
Solution Approach 2:
The patent employs composite material structures including glass substrates with metal traces, glass frit adhesives with specific compositions, and layered configurations of glass and electronic components. These composite structures are designed to optimize both thermal matching and manufacturing properties.
2Device complexity
If polymer substrates are used for electronic component packaging, then device complexity is reduced, but signal loss increases at high frequencies due to dielectric constant
Solution Approach 1:
The patent changes the dielectric parameter by substituting polymer materials with glass materials. Glass substrates and glass frit adhesives exhibit superior dielectric properties with lower loss tangents and more stable dielectric constants across high frequency ranges, thereby reducing signal loss while maintaining relatively simple package structures.
3Reliability
If individual packaging of electronic components is used, then reliability is improved through separate protection, but form factor increases and processing delays occur
Solution Approach 1:
The patent merges multiple electronic components onto a single glass substrate within a unified package structure. The glass substrate serves as a common platform for mounting multiple components, reducing the overall form factor while maintaining individual component protection and electrical isolation through glass frit adhesives and trace routing.
Solution Approach 2:
The patent utilizes three-dimensional packaging arrangements on the glass substrate, stacking components and routing traces in multiple layers and dimensions. This dimensional approach allows multiple components to be integrated within a compact volume while maintaining reliable electrical connections and reducing processing delays through shorter inter-component paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes the form factor, reduces latency delays, and decreases thermal stress and signal loss by closely matching the thermal expansion coefficient of the components and providing a stable dielectric environment, enhancing overall packaging efficiency.
Implementation Method 1
the upper glass cladding layer and the lower glass cladding layer have a higher etch rate in an etchant than the glass core layer
Data Source
AI summary
An electronic package assembly includes a glass substrate including an upper glass cladding layer, a lower glass cladding layer, a glass core layer coupled to the upper glass cladding layer and the lower glass cladding layer, where the upper glass cladding layer and the lower glass cladding layer have a higher etch rate in an etchant than the glass core layer, a first cavity positioned within one of the upper glass cladding layer or the lower glass cladding layer, and a second cavity positioned within one of the upper glass cladding layer or the lower glass cladding layer, a microprocessor positioned within the first cavity, and a micro-electronic component positioned within the second cavity.