Structured LDPC Coding for Parallel Decoding and Lower Storage
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Solution Overview
Problem
Low Density Parity Check (LDPC) codes are not widely deployed due to their complexity in encoding and decoding, high storage requirements, and computational load, particularly in check node operations, which hinders efficient implementation in communication systems.
Innovation Solution
A method for encoding and decoding information bits using structured LDPC codes with a parity check matrix represented in a tabular format, allowing for efficient memory access and parallelizable decoding, simplifying operations such as addition and table look-ups, and reducing storage needs by using parity bit accumulators and specific accumulator addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If LDPC encoding is implemented using generator matrix, then encoding capability is achieved, but storage complexity increases due to large non-sparse matrix requirements
Solution Approach 1:
The patent segments the large non-sparse generator matrix into multiple smaller sparse sub-matrices arranged in a specific structure. This segmentation allows the system to achieve the same encoding capability while significantly reducing storage requirements, as each sub-matrix can be stored efficiently and processed independently through parallel operations.
Solution Approach 2:
The patent applies local quality by making different parts of the encoding system have different properties - the sub-matrices are designed with specific sparsity patterns and structures that optimize both storage efficiency and processing speed. Each sub-matrix region serves a specific functional purpose in the overall encoding process.
2Reliability
If LDPC codes use large blocks to be effective, then error correction performance improves, but storage complexity increases for parity check matrices
Solution Approach 1:
The patent divides the large-scale LDPC code into multiple smaller code blocks, each with its own sparse parity check sub-matrix. This segmentation maintains the error correction performance of large blocks while reducing storage requirements, as each sub-matrix can be stored and processed independently rather than requiring storage of one massive dense matrix.
Solution Approach 2:
The patent transforms the storage problem from a two-dimensional large matrix into a multi-dimensional structure of smaller sub-matrices arranged in a specific pattern. This dimensional transformation allows efficient storage through the sparse structure of each sub-matrix while maintaining the overall code performance.
3Measurement precision
If check node operations are performed in LDPC decoding, then decoding accuracy improves, but computational load increases
Solution Approach 1:
The patent segments the decoding process into multiple independent check node operations corresponding to different sub-matrices. This segmentation enables parallel processing of check node operations, maintaining decoding accuracy while reducing the computational load on any single processing unit and enabling efficient implementation through parallel architectures.
Solution Approach 2:
The patent introduces dynamic parallel processing capabilities where multiple check node operations can be executed simultaneously based on the segmented sub-matrix structure. This dynamic approach allows the system to adapt computational resources to maintain accuracy while optimizing the computational load distribution across parallel processing elements.
4Ease of operation
If connection network between processing engines is established in decoder, then decoding functionality is achieved, but device complexity increases
Solution Approach 1:
The patent segments the decoder into multiple independent processing engines, each responsible for specific sub-matrix operations. This segmentation simplifies the connection network between processing engines, as each engine operates independently on its assigned sub-matrix data, requiring minimal inter-engine communication compared to a monolithic decoder architecture.
Solution Approach 2:
The patent designs processing engines with universal functionality that can handle different sub-matrix operations. This multi-functionality reduces the need for specialized connection networks between engines, as each engine can process various types of operations independently, simplifying the overall system architecture.
Data Source
AI summary
An approach is provided for encoding a source signal based on a structured parity check matrix of a Low Density Parity Check (LDPC) code. The LDPC code is represented by stored information reflecting a tabular format of rows and columns, wherein each row represents occurrences of one values within a respective column of the parity check matrix, and wherein the columns of the parity check matrix are derived according to an operation based on the respective rows of the stored information. Blocks of information bits of the source signal are encoded based on the LDPC code to generate an encoded signal. Row indices of 1's in a column index of the parity check matrix are given at a respective row according to the stored information. The LDPC code is of a structure that facilitates use of a plurality of parallel engines for decoding the encoded signal.