Structured Passivation in III-V HEMTs for Lower Dynamic RDS(on)
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Solution Overview
Problem
Current high-electron-mobility transistors face challenges in maintaining low dynamic on-state resistance (R DSON) without compromising static device parameters such as threshold voltage (Vth) and gate-source leakage current (IGSS) in power switching applications.
Innovation Solution
The design incorporates a semiconductor body with a barrier and channel region of type III-V semiconductor material forming a heterojunction, along with source and drain electrodes and a gate structure, where passivation regions with different dielectric materials are used to modulate the two-dimensional charge carrier gas density, specifically using aluminum oxide and silicon-based insulators to optimize R DSON without increasing gate-to-drain capacitance or electric fields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional passivation structures are used in HEMT devices, then device fabrication is simplified, but dynamic on-state resistance (R DSON) increases and power dissipation worsens
Solution Approach 1:
The passivation structure is divided into multiple distinct regions: a first passivation region over the barrier region with a first dielectric material, and a second passivation region over the channel region with a second dielectric material. This segmentation allows each region to be optimized independently for its specific function, reducing overall power dissipation while maintaining manageable fabrication complexity through systematic design.
Solution Approach 2:
Different dielectric materials are applied to different regions of the device based on local requirements. The first dielectric material is used where it optimally passivates the barrier region, while the second dielectric material is used where it optimally passivates the channel region. This local optimization enables reduced R DSON and improved power dissipation characteristics without requiring complete structural redesign.
2Manufacturing precision
If passivation regions are added to modulate charge carrier gas density, then sheet resistance in drain region is reduced, but device fabrication complexity increases
Solution Approach 1:
The passivation structure is divided into multiple distinct regions: a first passivation region over the barrier region with a first dielectric material, and a second passivation region over the channel region with a second dielectric material. This segmentation allows each region to be optimized independently for its specific function, reducing overall power dissipation while maintaining manageable fabrication complexity through systematic design.
Solution Approach 2:
Different dielectric materials with distinct electrical properties are employed in different regions to precisely control the charge carrier gas density and sheet resistance. By changing the material parameter (dielectric constant, interface trap density) in specific locations, the invention achieves superior electrical control without requiring excessive structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively lowers the sheet resistance in the drain region while maintaining favorable static parameters, improving power dissipation in both hard and soft switching applications without detrimental impacts on electric fields or gate leakage.
Implementation Method 1
a barrier region of type III-V semiconductor material and a channel region of type III-V semiconductor material that forms a heterojunction with the barrier region such that a two-dimensional charge carrier gas channel is disposed in the channel region near the heterojunction
Implementation Method 2
first and second passivation regions disposed on the semiconductor body, wherein the first and second passivation regions are arranged to influence the two-dimensional charge carrier gas such that a density of the two-dimensional charge carrier gas underneath an interface between the first passivation region and the semiconductor body is higher than underneath an interface between the second passivation region and the semiconductor body
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3B
AI summary
A high-electron-mobility transistor comprises a semiconductor body comprising a barrier region (104) and a channel region (106) that forms a heterojunction with the barrier region such that a two-dimensional charge carrier gas channel (110) is disposed in the channel region, source (120) and drain (122) electrodes disposed on the semiconductor body and laterally spaced apart from one another, a gate structure (124) disposed on the semiconductor body and laterally between the source and drain electrodes, the gate structure being configured to control a conduction state of two-dimensional charge carrier gas, and a first dielectric region (130) that is disposed along the upper surface of the semiconductor body in a lateral region that is between the gate structure and the drain electrode, wherein the first dielectric region comprises aluminum and oxide, and wherein first dielectric region comprises a first end (132) that faces and is laterally spaced apart from the gate structure.