Structured Skewing Buffering for CMOS Imager Timing Convergence
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Solution Overview
Problem
The tree type routing scheme in CMOS imager circuits often requires too many line buffers, leading to poor performance and high peak current due to its inefficiency in designs with large/small aspect ratios, resulting in inadequate timing convergence and increased risk of area congestion.
Innovation Solution
A structured skewing buffering method that calculates and arranges line buffers based on average branches and stages, forming a flexible fish bone structure to reduce the number of buffer stages and peak power consumption, allowing for tailored topology implementation that balances propagation delay and vertical routing area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If tree type routing scheme is used to implement long signal lines, then timing convergence and automatic placement are improved, but the number of line buffers increases excessively, resulting in poor performance and high peak current
Solution Approach 1:
The patent segments the signal line into multiple sections with different buffering strategies. Instead of uniformly applying tree type routing throughout, it divides the line into segments where repeat line buffers are placed at specific intervals (e.g., every 50-200 micrometers) rather than using the hierarchical tree structure, thereby reducing the total number of buffers while maintaining timing convergence in critical sections.
Solution Approach 2:
The patent applies different buffering characteristics to different sections of the signal line based on local requirements. Critical sections with tight timing constraints receive repeat line buffers at shorter intervals, while non-critical sections use longer intervals or no buffering. This localized approach optimizes performance without unnecessarily increasing the total buffer count across the entire line.
2Reliability
If repeat line buffers are placed frequently to meet timing constraints, then signal integrity is maintained, but peak current increases due to simultaneous switching of multiple buffers
Solution Approach 1:
The patent introduces periodic non-repeat sections where no line buffers are placed, creating a rhythmic pattern of buffered and unbuffered sections along the signal line. This periodic structure allows buffers to switch at staggered times rather than simultaneously, reducing peak current while maintaining signal integrity in the buffered sections. The period of this pattern can be adjusted based on the specific timing and power constraints of the design.
3Ease of manufacture
If tree type routing scheme is used for large aspect ratio designs, then routing is automated, but area congestion increases and performance deteriorates
Solution Approach 1:
The patent inverts the conventional approach by not using automatic tree type routing generation, but instead manually specifying buffer locations based on design constraints and performance requirements. This inversion allows designers to optimize buffer placement for large aspect ratio layouts, preventing area congestion while still achieving automatic placement through constrained optimization algorithms that respect the specified buffer locations and routing rules.
Data Source
AI summary
A line buffering technique in which a plurality of line buffers are arranged based on a determined average number of branches and stages that are necessary to implement the buffers based on design constraints. In an exemplary embodiment, the line buffers may be arranged in any buffer topology arrangement meeting the average number of branches and the number of stages design constraints.