STT Memory Write Control Logic for Asymmetric Latency
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Solution Overview
Problem
Spin transfer torque (STT) memory systems face challenges in managing write operations efficiently, leading to asymmetric write latency, which affects the performance of nonvolatile memory systems.
Innovation Solution
The implementation of successive, selective write operations on each row in STT memory, where memory cells are switched from anti-parallel to parallel or vice versa, with voltage control to minimize latency, using a write control logic that configures word lines and bit lines to apply specific voltages for each state transition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional write operations are used in STT memory, then write operations can be performed, but asymmetric write latency occurs affecting performance
Solution Approach 1:
The write operation is segmented into two distinct phases: a first write operation for transitioning memory cells from anti-parallel to parallel state, and a second write operation for transitioning memory cells from parallel to anti-parallel state. This segmentation allows each phase to be optimized independently, resolving the asymmetric latency issue by handling different state transitions separately rather than as a single unified operation.
Solution Approach 2:
The patent implements dynamic voltage control where different voltages are applied to word lines and bit lines depending on the desired state transition. The write control logic dynamically adjusts the voltage levels based on the current state and target state of memory cells, enabling optimized write speeds for different transition types and eliminating the fixed asymmetric latency of conventional approaches.
2Loss of time
If voltage control is applied to control state transitions, then write latency is minimized, but device complexity increases due to write control logic
Solution Approach 1:
The write control logic is designed to perform multiple functions: it manages both first and second write operations, controls voltages for different state transitions, and coordinates word lines and bit lines. By making the control logic universal and multi-functional, the patent reduces the need for separate dedicated control circuits for each write operation type, thereby minimizing the increase in device complexity while achieving minimized write latency through dynamic voltage control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces or eliminates asymmetric write latency, enhancing the efficiency of write operations in STT memory systems by allowing for precise control of state transitions in memory cells.
Implementation Method 1
Spin transfer torque (STT) memory is developing as a technology for nonvolatile memory systems
Data Source
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AI summary
Apparatus, systems, and methods for write operations in spin transfer torque (STT) memory are described. In one embodiment, a controller comprises logic to identify a first plurality of cells in a row of spin transfer torque (STT) memory which are to be set to a parallel state and a second plurality of cells in the row of the STT memory which are to be set to an anti-parallel state, mask write operations to the second plurality of cells in the row, set the first plurality of cells to a parallel state, mask write operations to the first plurality of cells in the row, and set the second plurality of cells to an anti-parallel state. Other embodiments are also disclosed and claimed.