STT-MRAM Bit Cell Layout and Write Control Logic
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Solution Overview
Problem
Conventional Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) faces scalability issues due to increasing current density and power consumption as bit cells become smaller, and existing circuit designs are inefficient in terms of area usage, leading to potential invalid write operations in unselected bit cells.
Innovation Solution
The solution involves rearranging word lines and source lines in a parallel and perpendicular configuration to reduce bit cell size, allowing for shared source lines and implementing write control logic to prevent invalid writes by setting unselected bit lines to a high impedance state during write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bit cell size is reduced to increase memory density, then memory capacity is improved, but current density and power consumption increase
Solution Approach 1:
The patent combines the source line and bit line into a single shared line structure. The source line serves dual functions as both source line and bit line for different operations, reducing the number of separate conductors needed and thereby reducing overall power consumption while maintaining memory density
Solution Approach 2:
The shared line is designed to perform multiple functions: serving as a source line during write operations and as a bit line during read operations. This multi-functionality reduces the total number of lines required, decreasing capacitive loading and power consumption while achieving high memory density
2Ease of manufacture
If conventional circuit design is used, then ease of manufacture is maintained, but area usage efficiency decreases and invalid write operations occur
Solution Approach 1:
The patent implements dynamic control of the shared line through write enable signals that switch the line between source and bit line functions. Write control logic dynamically prevents invalid write operations by controlling the impedance state of unselected bit cells, enabling efficient space usage without sacrificing manufacturability
Solution Approach 2:
Write control logic acts as an intermediary between the write signals and the memory cells, preventing invalid write operations to unselected cells by controlling the impedance state of shared lines. This mediator ensures correct operation while enabling compact cell design
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces bit cell size, prevents invalid write operations, and maintains write stability by optimizing the layout and logic for STT-MRAM arrays, enhancing scalability and operational efficiency.
Implementation Method 1
Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) uses electrons that become spin-polarized as the electrons pass through a thin film (spin filter). During the write operation, the spin-polarized electrons exert a torque on the free layer, which can switch the polarity of the free layer.
Implementation Method 2
Due to the tunnel magnetoresistive effect, the electrical resistance of the MTJ 100 changes based on the orientation of the polarities in the two magnetic layers (e.g., 110, 130), as discussed above.
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3A~3B
AI summary
Systems, circuits and methods for controlling write operations in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A reduced bit cell size is achieved by arranging the source lines (SL) substantially in parallel with the word lines (WL) and substantially perpendicular to the bit lines (BL). Further, in one embodiment during a write operation, a high logic / voltage level is applied to the bit lines of unselected bit cells to prevent an invalid write operation.