STT-MRAM Bit Defect Detection and Redundancy Remapping
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Solution Overview
Problem
Conventional error correction schemes for STT-MRAM memory devices are inefficient in real-time detection and correction of bit defects, particularly at high defect rates, as they require significant overhead for storing defective bit locations and do not correct errors as data is written, leading to potential system crashes and data corruption.
Innovation Solution
The implementation of a method that uses redundant bits added to each codeword in STT-MRAM memory, where defective bits are mapped and replaced with redundant bits in real-time during both write and read operations, eliminating the need for storing defective bit locations and enabling on-the-fly correction without large peripheral circuit overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction schemes are used to detect and correct bit defects in STT-MRAM memory, then data integrity can be maintained, but significant overhead is required for storing defective bit locations and the correction is not performed in real-time
Solution Approach 1:
The patent applies preliminary action by performing a read operation before the write operation to detect defective bits in advance. The system reads the codeword, identifies defective bits through mapping, and replaces them with redundant bits before the actual write occurs. This proactive approach ensures data integrity is maintained without requiring complex overhead structures during normal operation.
Solution Approach 2:
The patent uses redundant bits as an intermediary mechanism to replace defective bits. Instead of directly storing and managing complex defect location information, the system introduces redundant bits that serve as substitutes for defective positions. This intermediary approach simplifies the error correction process while maintaining data integrity.
2Reliability
If conventional error correction schemes are used, then bit defects can be corrected, but the correction is not performed during write operations leading to potential system crashes and data corruption
Solution Approach 1:
The system performs error detection and correction as a preliminary step before the write operation completes. By reading the codeword, identifying defective bits, and replacing them with redundant bits before the actual data write, the system ensures correction happens in real-time during the write process, preventing system crashes and data corruption.
Solution Approach 2:
The patent merges the error correction function with the write operation itself. Instead of separating correction into a post-processing step, the system combines reading, defect detection, bit replacement, and writing into an integrated process. This merging enables real-time correction without adding separate correction steps that would cause delays.
3Reliability
If redundant bits are added to each codeword for defect replacement, then real-time correction is enabled, but memory structure complexity increases
Solution Approach 1:
The redundant bits serve multiple functions: they act as substitutes for defective bits during error correction, and they are integrated into the normal codeword structure. This multi-functionality allows the memory structure to handle errors while maintaining compatibility with standard memory operations, reducing the perceived complexity increase.
Solution Approach 2:
The patent applies local quality by adding redundancy specifically at the bit level within codewords rather than requiring global structural changes. Each codeword is enhanced locally with redundant bits that are positioned and managed according to specific mapping schemes, allowing real-time correction without fundamentally altering the overall memory architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for real-time detection and correction of bit defects, reducing the likelihood of system crashes and data corruption, increasing memory reliability, and extending the lifespan of the memory chip by continuously correcting defects over its operational lifetime without the need for extensive overhead.
Implementation Method 1
Due to the spin-polarized electron tunneling effect, the electrical resistance of the cell change due to the orientation of the magnetic fields of the two layers
Implementation Method 2
If a spin-polarized current is passed to the magnetic region of a free layer in the magnetic tunnel junction device, the electrons will transfer a portion of their spin-angular momentum to the magnetization layer to produce a torque on the magnetization of the free layer
Implementation Method 3
The electrical resistance is typically referred to as tunnel magnetoresistance (TMR) which is a magnetoresistive effect that occurs in a MTJ
Data Source
AI summary
A method for correcting bit defects in an STT-MRAM memory is disclosed. The method comprises executing a read before write operation in the STT-MRAM memory, wherein the STT-MRAM memory comprises a plurality of codewords, wherein each codeword comprises a plurality of redundant bits. The read before write operation comprises reading a codeword and mapping defective bits in the codeword. Further, the method comprises replacing the defective bits in the codeword with a corresponding redundant bit and executing a write operation with corresponding redundant bits in place of the defective bits.