STT-MRAM Cell Doped Silicon Buffer for Source Degeneration

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Solution Overview

Problem

Conventional STT-MRAM structures face limitations due to the source degeneration effect, which restricts the reliable switching of magnetization direction from parallel to anti-parallel, and existing solutions are not scalable for modern consumer electronic devices with tight spacing requirements.

Innovation Solution

The proposed STT-MRAM structure includes a word line layer, a bit line metal layer, and an MRAM stack with a doped silicon layer configuration that separates the MTJ layer from the source line, using conductivity-determining ions of specific types to prevent source degeneration and maintain a small cell size, while the source line is in electrical contact with the doped silicon layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional STT-MRAM structure with source line directly connected to MTJ is used, then the device complexity is reduced, but the source degeneration effect prevents reliable switching of magnetization from anti-parallel to parallel

Engineering Contradiction:

Improvereliable switching of magnetizationVSAvoiddoped silicon layer configuration

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a doped silicon layer as an intermediary component between the source line and the MTJ structure. This intermediary layer, configured with specific doping types and patterns, mediates the current flow to eliminate the source degeneration effect while maintaining reliable magnetization switching. The doped silicon layer acts as a buffer that prevents the harmful interaction between the source line and MTJ that causes switching failures.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Quantity of substance

If the cell size is reduced to increase memory density, then the memory cell density increases, but the spacing becomes too tight for existing MTJ structures

Engineering Contradiction:

Improvememory cell densityVSAvoidwrite disturbances

Core Design Contradiction:

Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The patent employs a vertical stacking architecture where the doped silicon layer is positioned at a different vertical level between the source line and the MTJ stack. This dimensional separation allows for tighter horizontal spacing of memory cells while maintaining adequate electrical isolation and preventing write disturbances. The vertical arrangement enables higher cell density without compromising the functional integrity of each cell.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Reliability

If high programming current is used to switch magnetization states, then the switching reliability is improved, but write disturbances affect adjacent cells

Engineering Contradiction:

Improveswitching reliabilityVSAvoidwrite disturbances

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The doped silicon layer is selectively positioned and doped with specific conductivity types in different regions to locally control current flow paths. By creating non-uniform doping patterns and conductivity distributions, the structure guides the programming current precisely through the target MTJ cell while preventing current leakage into adjacent cells, thus eliminating write disturbances while maintaining switching reliability.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively addresses the source degeneration problem, ensuring reliable switching and scalability, while maintaining a compact design suitable for modern consumer electronics by reducing the footprint and preventing write disturbances.

Implementation Method 1

spin torque transfer magnetic random access memory (STT-MRAM) structures

Methodology Applied

Scientific EffectSpin torque transfer:

Implementation Method 2

Magnetic Random Access Memory (MRAM) is a non-volatile computer memory technology based on magnetoresistance

Methodology Applied

Scientific EffectMagnetoresistance: Magnetoresistance

Implementation Method 3

a first doped silicon layer including conductivity-determining ions of a first type

Methodology Applied

Scientific EffectDoping: Dopants

Data Source

PatentUS9484530B2Integrated circuit structures with spin torque transfer magnetic random access memory having increased memory cell density and methods for fabricating the same

Publication Date: 2016.11.01 GLOBALFOUNDRIES SINGAPORE PTE LTD

AI summary

STT-MRAM integrated circuit and method for fabricating the same are disclosed. An integrated circuit includes a word line layer, a bit line layer, and an MRAM stack in contact with the bit line metal layer. The integrated circuit further includes a first doped silicon layer in contact with the MRAM stack, the first doped silicon layer including conductivity-determining ions of a first type, and a second doped silicon layer in contact with the first doped silicon layer and further in contact with the word line layer, the second doped silicon layer including conductivity-determining ions of a second type that is opposite the first type. Still further, the integrated circuit includes a third doped silicon layer in contact with the second doped silicon layer and a source line layer in electrical contact with the third doped silicon layer.