STT-MRAM Error Cache with Dynamic Redundancy Registers
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Solution Overview
Problem
Conventional STT-MRAM devices lack structures to track write errors and manage power consumption, leading to unreliable memory due to high write error rates and the potential for overflow in error tracking mechanisms.
Innovation Solution
The implementation of dynamic redundancy registers, specifically an e1 register and an optional e2 register, which allow for error tracking, re-write operations, and data relocation without impacting throughput or requiring dual-port memory cells, enabling transparent re-write attempts only when the memory bank is idle and using non-volatile or volatile memory technologies to ensure data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error tracking structures are added to STT-MRAM devices, then reliability is improved, but device complexity increases
Solution Approach 1:
The error tracking system is nested within the existing memory bank structure. The error buffer and control logic are integrated into the memory bank, allowing error tracking functionality to be embedded without requiring a completely separate system architecture. This nesting approach improves reliability by providing error tracking while minimizing the increase in overall device complexity.
Solution Approach 2:
An error buffer acts as an intermediary structure between the memory bank and the control logic. This intermediary component captures write errors temporarily and allows for coordinated error handling, improving reliability without directly complicating the core memory structure. The error buffer serves as a buffer zone that manages error information flow.
2Reliability
If error tracking mechanisms are implemented, then write error management is improved, but power consumption increases
Solution Approach 1:
The error tracking system employs dynamic power management where the error buffer and associated control logic can be selectively activated or deactivated based on operational needs. During normal write operations, the error tracking functionality remains active to capture errors, but can be dynamically adjusted to reduce power consumption when error tracking is less critical, thus balancing reliability improvement with power efficiency.
3Reliability
If re-write operations are performed transparently, then data integrity is improved, but throughput may be impacted
Solution Approach 1:
The system performs preliminary error checking and buffering of write operations before final commitment to the memory bank. By pre-processing write operations and identifying errors early in the pipeline, the system can initiate re-write operations without significantly impacting overall throughput. The error buffer holds intermediate results, allowing re-write operations to be scheduled efficiently.
Solution Approach 2:
The patent replaces complex mechanical coordination of dual-port memory cells with a software-controlled error buffer and control logic system. This substitution allows re-write operations to be managed through logical control rather than complex hardware timing mechanisms, maintaining data integrity while simplifying the control architecture and reducing overhead that would impact throughput.
4Adaptability or versatility
If dual-port memory cells are used for re-write operations, then re-write capability is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts the re-write capability from the memory cell structure itself and places it in a separate error buffer and control logic system. Instead of requiring dual-port memory cells, the system uses a single-port memory bank with an external error buffer that manages re-write operations. This extraction approach provides full re-write capability while using simpler, less expensive single-port memory cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows STT-MRAM devices to operate reliably with high write error rates by transparently managing re-write operations and maintaining data integrity, even during power down, by utilizing dynamic redundancy registers that prioritize reliability and efficient power management.
Implementation Method 1
Due to the spin-polarized electron tunneling effect, the electrical resistance of the cell changes due to the orientation of the magnetization of the two layers.
Implementation Method 2
one of the plates has its magnetization pinned (i.e., a 'reference layer'), meaning that this layer has a higher coercivity than the other layer
Implementation Method 3
The e1 register stores a data word and an associated address for data words in a memory bank that have not had an opportunity to verify
Data Source
AI summary
A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. The memory device also comprises a cache memory operable for storing a second plurality of data words, wherein further each data word of the second plurality of data words is either awaiting write verification or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments of the memory bank, wherein each primary segment of the plurality of primary segments of the cache memory is sub-divided into a plurality of secondary segments, and each of the plurality of secondary segments comprises at least one counter for tracking a number of valid entries stored therein.