Dynamic Redundancy Registers for STT-MRAM Error Cache Management
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Solution Overview
Problem
Conventional STT-MRAM devices lack structures to track write errors and manage power consumption, leading to unreliable memory due to high write error rates and potential overflow in error tracking mechanisms.
Innovation Solution
The implementation of dynamic redundancy registers, specifically e1 and e2 registers, which allow for transparent re-write operations without delaying read/write operations, manage error tracking, and optimize power usage by relocating data during idle memory bank cycles and utilizing non-volatile memory for reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error tracking structures are added to STT-MRAM devices, then reliability improves, but device complexity increases
Solution Approach 1:
The memory bank is divided into multiple segments, and the error cache is divided into corresponding segments that track errors for each memory segment. This segmentation allows distributed error tracking without requiring a single complex centralized error tracking structure, reducing overall device complexity while maintaining reliability.
Solution Approach 2:
An error cache (e1 register) is introduced as an intermediary structure between the memory bank and the control logic. This error cache temporarily stores error information and coordinates the interaction between memory operations and error handling, simplifying the overall system architecture while enabling comprehensive error tracking.
2Reliability
If error tracking mechanisms are implemented, then data integrity improves, but power consumption increases
Solution Approach 1:
Error cache clearing is performed periodically based on occupancy thresholds rather than continuously. The system monitors error cache occupancy and clears it when thresholds are reached, enabling power-efficient error tracking by activating error handling logic only when necessary rather than maintaining constant error checking and clearing operations.
Solution Approach 2:
Different segments of the error cache can be cleared independently based on local occupancy conditions. This allows power consumption to be optimized by clearing only the necessary segments rather than the entire error cache, reducing overall power usage while maintaining data integrity in all segments.
3Use of energy by moving object
If coarse grain segments are used in error cache, then power consumption decreases, but measurement precision of error tracking worsens
Solution Approach 1:
The error cache is divided into multiple segments corresponding to memory bank segments. This segmentation provides a middle ground between coarse and fine grain tracking, allowing power-efficient operation by clearing segments independently while maintaining sufficient precision to track errors in each memory segment separately.
Solution Approach 2:
The system can dynamically adjust error cache management parameters such as occupancy thresholds and segment clearing strategies based on operational conditions. This allows optimization of the balance between power consumption and error tracking precision by changing operational parameters rather than fixed structural properties.
4Measurement precision
If fine grain segments are used in error cache, then error tracking precision improves, but power consumption increases
Solution Approach 1:
Even with fine-grain segmentation, the system uses periodic clearing based on occupancy thresholds rather than continuous operation. This reduces power consumption by activating error handling logic only when error caches approach capacity, maintaining high tracking precision while avoiding constant power usage.
Solution Approach 2:
Fine-grain segments allow independent management of different error cache regions. Power consumption is optimized by clearing only the segments that need clearing based on local occupancy conditions, rather than clearing the entire error cache, thus maintaining precision while reducing overall power usage.
5Reliability
If error cache occupancy increases, then error tracking capability improves, but overflow risk increases
Solution Approach 1:
The system implements periodic error cache clearing based on occupancy thresholds. When error cache occupancy reaches predetermined thresholds, the cache is automatically cleared, preventing overflow while maintaining error tracking capability. This periodic clearing mechanism ensures the error cache operates within safe occupancy limits.
Solution Approach 2:
The system monitors error cache occupancy and uses this feedback to trigger clearing operations when thresholds are reached. This feedback mechanism dynamically adjusts error cache management to prevent overflow while maximizing error tracking capability, clearing the cache only when necessary based on actual occupancy levels.
6Reliability
If re-write operations are implemented, then data reliability improves, but throughput decreases
Solution Approach 1:
The error cache serves as an intermediary that buffers re-write operations from impacting main memory throughput. By coordinating re-write attempts through the error cache and using periodic clearing, the system can perform necessary re-writes for reliability while minimizing disruptions to the overall memory throughput.
Solution Approach 2:
The system can adjust re-write operation parameters such as the number of retry attempts and timing based on error cache occupancy and error patterns. This allows optimization of the balance between reliability (through adequate re-write attempts) and throughput (by avoiding excessive retries), dynamically changing operational parameters based on system state.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables STT-MRAM devices to operate with high write error rates without throughput or speed loss, ensuring data integrity and efficient power management, even during power transitions.
Implementation Method 1
Due to the spin-polarized electron tunneling effect, the electrical resistance of the cell changes due to the orientation of the magnetization of the two layers.
Data Source
AI summary
A memory device comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. Further, the device comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments, wherein each primary segment is sub-divided into a plurality of secondary segments, and wherein each of the plurality of secondary segments comprises at least one counter for tracking a number of entries stored therein.